Structured Datapath Physical Block Design Lead Engineer

Intel Corp. Hillsboro , OR 97123

Posted 2 months ago

Structured Datapath Physical Block Design Lead EngineerJob Description

As a Physical Block Design Engineering Lead, your responsibilities include:

  • Logic design, circuit design, and layout of high-speed digital logic blocks.

  • Working with senior designers and micro-architects to complete detailed circuit, timing, power and layout studies, from placement and wire planning.

  • Timing convergence, power convergence, functional equivalence verification, and layout verification

  • Coordinating, training, and mentoring other engineers to accomplish

  • Attention to quality and reliability at the circuit and layout level

As an ideal candidate you exhibit behavioral traits that indicate your:

  • Ability to use sound methods and data to test new ideas as well as the desire to have your own ideas be challenged by others.

  • Willingness to work with others inside and outside your organization in a highly complex decision space.

  • Strong verbal and written communication and collaboration skills.

  • Leadership by providing training, mentoring, and providing technical help to other engineers to help them grow and develop in their ability as well as help them to deliver their designs on schedule and with high quality

  • Ability to delegate and follow up


Minimum Qualifications:

  • Bachelors in Computer Engineering, or Electrical Engineering with 6+ years of relevant work experience OR M.S. in Computer Engineering, or Electrical Engineering with 4+ years of relevant work experience

  • Experience with integrated circuit design tools, including schematic capture, logic synthesis, place and route, static timing analysis and design closure

  • Understanding of different design styles on the die including memories.

  • Scripting in an interpreted language (e.g. Perl, Python, TCL, Ruby)

Demonstrated success in one or more of the following areas:

  • Custom digital logic block design

  • Synthesis of a digital logic block, which was integrated into a large SoC or IP

  • Static timing convergence and dynamic power convergence

Preferred Qualifications:

  • Intel CPU/Microprocessor design experience

  • Design of a high-speed CPU core logic block

  • Understanding of advanced processes' layout design rules.

Inside this Business Group

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance..

See if you are a match!

See how well your resume matches up to this job - upload your resume now.

Find your dream job anywhere
with the LiveCareer app.
Download the
LiveCareer app and find
your dream job anywhere

Boost your job search productivity with our
free Chrome Extension!

lc_apply_tool GET EXTENSION

Similar Jobs

Want to see jobs matched to your resume? Upload One Now! Remove
Design Verification Engineer (Bfm /C / Verilog )

Redolent, Inc

Posted 2 days ago

VIEW JOBS 11/14/2018 12:00:00 AM 2019-02-12T00:00 <style type="text/css"><!--td {border: 1px solid #ccc;}br {mso-data-placement:same-cell;}--> </style> <strong>We have following urgent role with our  DIRECT client</strong><br /> <br /> <strong>Title: Design Verification Engineer (BFM /C / Verilog )</strong><br /> <strong>LOCATION: Hillsboro, OR <br /> DURATION: 6+ months <br /> Compensation: Competitive ( DOE )</strong><br /> <br /> <br /> <strong>Job Description:</strong> <ul> <li style="padding: 0px; margin: 0px;" style="padding: 0; margin: 0;">Experience in  <strong>C or SystemC </strong>modeling experience in addition to <strong>Design Verification</strong> experience. <br /> 5+ years, familiar with <strong>Verilog</strong>/System Verilog simulator DPI. </li> <li style="padding: 0px; margin: 0px;" style="padding: 0; margin: 0;">Experience with <strong>BFM </strong>( <strong>BUS Functional Module</strong> ), which synonymous to Verification IP or <strong>VIP</strong>.</li> </ul> <br /> <style type="text/css"><!--td {border: 1px solid #ccc;}br {mso-data-placement:same-cell;}--> </style> Redolent, Inc Hillsboro OR

Structured Datapath Physical Block Design Lead Engineer

Intel Corp.