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Static Timing Engineer

Expired Job

Apple Inc. Santa Clara , CA 95051

Posted 5 months ago

Job Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and transfix millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers.

Key Qualifications

This position requires thorough knowledge of the ASIC design timing closure flow and methodology. The ideal candidate will have the following background: - At least 2+ year's experience in ASIC timing constraints generation and timing closure

  • Expertise in STA tools (Primetime) and flow

  • Knowledge of timing corners/modes, process variations and signal integrity related issues

  • Hands on experience in timing/SDC constraints generation and management

  • Proficient in scripting languages (Tcl and Perl) - Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools

  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups

  • Self-starter and highly motivated


As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design: - Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation) - Develop and maintain methodology and flows related to timing verification and closure

  • Generation of block and full chip timing constraints


BS EE, EECS, or CS is required

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Static Timing Engineer

Expired Job

Apple Inc.