Sorry, this job is no longer accepting applications. See below for more jobs that match what you’re looking for!

Static Timing Engineer

Expired Job

Apple Inc. Santa Clara , CA 95051

Posted 3 months ago

Job Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and transfix millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers.

Key Qualifications

This position requires thorough knowledge of the ASIC design timing closure flow and methodology. The ideal candidate will have the following background: - At least 2+ year's experience in ASIC timing constraints generation and timing closure

  • Expertise in STA tools (Primetime) and flow

  • Knowledge of timing corners/modes, process variations and signal integrity related issues

  • Hands on experience in timing/SDC constraints generation and management

  • Proficient in scripting languages (Tcl and Perl) - Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools

  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups

  • Self-starter and highly motivated

Description

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design: - Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation) - Develop and maintain methodology and flows related to timing verification and closure

  • Generation of block and full chip timing constraints

Education

BS EE, EECS, or CS is required


See if you are a match!

See how well your resume matches up to this job - upload your resume now.

Find your dream job anywhere
with the LiveCareer app.
Download the
LiveCareer app and find
your dream job anywhere
lc_ad

Boost your job search productivity with our
free Chrome Extension!

lc_apply_tool GET EXTENSION

Similar Jobs

Want to see jobs matched to your resume? Upload One Now! Remove
SOC Timing Design Engineer

Intel Corp.

Posted 4 days ago

VIEW JOBS 11/14/2018 12:00:00 AM 2019-02-12T00:00 SOC Timing Design EngineerJob Description * Job DescriptionOversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Qualifications BS or MS or PhD in Electrical Engineering, Computer Science, Computer Engineering, or other related field * 10+ years of hands-on experience track-record of success in pre-silicon and post-silicon physical design and validation to provide basis for management judgment and schedule management. * Strong technical leadership and communication skills; great team player. * Works well with senior technical and business experts * Data-driven decision making and balanced approach to enable technical analysis and solutions. * Self-starter, self-motivator, great problem solving skills and a passion for continuous improvement systems and improving overall design/group efficiency. Preferred Skills/Experience * hands on experience of major physical design tools such as Primetime, Calibre, Spyglass, ICC/ICC2 * strong scripting skills, must be familiar with one or more of the following: tcl/python/perl * Expertise in integrating different physical design flows; * solid circuit design fundamentals and techniques. Demonstrate good skills in timing and other physical design convergence Inside this Business Group Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.... Intel Corp. Santa Clara CA

Static Timing Engineer

Expired Job

Apple Inc.