Responsibilities: - As a Physical Design Engineer (Global Timing), you will be part of our Global Timing team and responsible for running/supporting/maintaining the Global Timing Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology.
Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the global timing flow and making sure all the blocks meet timing requirements.
Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools.
Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification.
Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
Experience in tape-outs of high performance SOC is highly desired.
Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation.
Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification.
Knowledge of scripting languages such as Perl/TCL is required.
Diligent, detail-oriented, and handle assignments with minimal supervision.
Must possess good communication skills, self-driven individual and a good team player.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.