Staff IC Design Engineer - Storage

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Data Storage SOC Mobile is exciting, rewarding and dynamic, with many opportunities for professional growth for a motivated candidate. As part of Marvell's Data Storage division we develop and implement the leading edge System-on-Chip solutions. You work closely with your peers, test engineers, field application engineers and product engineers to find the optimal and most cost efficient solution for our customers.

What You Can Expect

Responsibilities include design and integrate IPs for System-on-Chip solution using state-of-the-art IC design methodologies and design flows.

• Perform RTL coding.

• Perform functional verification of design on block and system level.

• Perform synthesis and timing closure.

• Perform ATPG and test pattern generation.

• Provide design documentation, description and information to application engineers, test engineers, production engineers, and customers.

What We're Looking For

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience. Or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.

• Must be familiar with digital IC design methodologies, understands all stages of ASIC design flows, and is experienced with state-of-the-art design tools.

• Strong in logic design and verification, and has solid knowledge of related VLSI architectures.

• Knowledge of RTL coding, Verilog preferred.

• Knowledge of verification of design at block and system level.

• Knowledge of logic synthesis and timing analysis.

• Knowledge of SCAN/DFT.

#LI-TM1

Expected Base Pay Range (USD)

102,800 - 154,000, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.