Marvell, a leading supplier of high performance storage networking solutions, has the following opening in its Server Connectivity Business Unit. This is position's primary function is the advanced verification of leading edge Fibre Channel SoCs. In this role you will be responsible for developing verification plans and architecting test benches to validate DUT (Device Under Test) functionality in simulation of application specific integrated circuit (ASIC/Integrated Circuit).
Interpreting architectural and design requirements
Writing verification test plans and requirements
Developing and using complex test benches
Implementing directed and constrained random test cases
Collecting, analyzing, and enhancing functional and code coverage
Debugging issues in the requirements, tools, simulation environment, test cases, and DUT - Performing Object Oriented programming (System Verilog and C++) - Participating in System Verilog Verification using a framework such asUVM or other industry standard methodologies
Extensive PCIe related pre- and post- silicon debug (HW lab debug and Simulation); and, Skills to use Logic analyzers and Oscilloscopes
Verification automation and scripting.
Use Perl / Shell / Python scripting skills and Extensive markup language XML to design/simulation environment automation.
Hardware / Firmware interaction and Firmware programming and knowledge of Microprocessors and assembly language
Knowledge of other industry standard protocol is plus. BS or MS (Electrical or Computer Engineering ) or Equivalent Degree with 8+ years of experience Proficient with SystemVerilog, HDL languages, Object Oriented Programming and Scripting Languages. #LI-TM1 #GLDR
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.