STA Engineer- San Jose

As an STA Engineer at iSoftTek Solutions Inc, you will be responsible for performing Static Timing Analysis (STA) for our clients' semiconductor designs. You will have the opportunity to work on cutting-edge technologies and collaborate with cross-functional teams to ensure the successful delivery of projects.

We are looking for a candidate who has strong knowledge and experience in STA methodologies and tools. The ideal candidate should be detail-oriented, have excellent problem-solving skills, and be able to thrive in a fast-paced and dynamic environment.

Role/ Responsibilities:

Lead-driven model: Top/Block level STA timing closure, SDC QC, SCRIPTING {TCL, PERL/PYTHON}, TOOL KNOWLEDGE {PRIMETIME, TWEAKER} , SDC writing.

Skills Required:

STA:  Good timing concepts, Good understanding of StarRC/Primetime or QRC/Tempus tool, Ability to understand timing reports, analyze and identify timing bottlenecks, exposure in timing closure flow

Tools: Primetime, Tempus, QRC and STAR-RC

Requirements

Requirements:

8 to 12 years of relevant experience in Static timing analysis.

Able to handle top-level, sub-system level, block level timing analysis and Fixes.

Expert in TCL or Python scripting.

Have experience in leading & Managing teams from different GEO’s.

Proficient in using industry-standard STA tools

Strong knowledge of EDA tools for synthesis, place and route, and physical design

Experience with clock domain crossing analysis

Knowledge of timing closure techniques and methodologies

Experience with scripting languages such as Tcl or Perl

Understanding of digital design principles and methodologies

Excellent analytical and problem-solving skills

Good communication and collaboration skills

BS or MS degree in Electrical Engineering or a related field