Sr. Staff Digital Design Engineer

Marvell Santa Clara , CA 95051

Posted 1 week ago

Marvell is a leading provider of innovative storage technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems.

Marvell demonstrates storage market leadership by continually innovating solutions that deliver the industry's highest performance and lowest power consumption with cost efficiency. With a vast portfolio of storage technology building blocks, innovative design, and packaging expertise, Marvell solutions enable customers to engineer high-volume products for hard disk drive (HDD), solid-state drive (SSD), cloud, enterprise, and data center.

We have an outstanding history of delivering next generation products that are revolutionizing the way the world works. We're looking for smart, talented, like-minded people to join us on the adventure. If you want to achieve great things, then we want to talk with you!

What You Will Be Doing

Our team is building key IPs in SSD controller such as the NVMe IP and the Flash Controller IP. These IPs decide the functions and performance of SSD controller. Due to the broad range of market targets, this team is required to make design flexible to support requirements from different market segments in a short period of time.

Your Key Responsibilities Will Include

  • This position will expose you to many important storage technologies such as high-performance interfaces with Host and NAND, as well as advanced LDPC error correcting technology.

  • This position in particular is focusing on NVMe IP. The challenge of this position as a Senior Staff Design Engineer is to have a deep understanding of the NVMe protocol and employ deep innovation to develop the next generation NVMe IP, with the latest features and improvements to both the performance and efficiency of the IP to a new level.

Education & Experience Necessary for Success

  • MSEE with 10+ years of experience in digital design

  • Strong knowledge of NVMe protocol

  • Strong knowledge of SSD controller architecture

  • RTL coding experience with the Verilog/SystemVerilog language.

  • Familiarity of ASIC design flow

  • Familiarity with Simulation and Synthesis tools and flow

  • Good communication and interpersonal skills

  • UVM based test bench development experience a plus

  • Scripting/programming language such as PERL/Python, TCL and C/C++ a plus

#LI-LH1

#GLDR

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


icon no score

See how you match
to the job

Find your dream job anywhere
with the LiveCareer app.
Mobile App Icon
Download the
LiveCareer app and find
your dream job anywhere
App Store Icon Google Play Icon
lc_ad

Boost your job search productivity with our
free Chrome Extension!

lc_apply_tool GET EXTENSION

Similar Jobs

Want to see jobs matched to your resume? Upload One Now! Remove
Senior Staff Digital IC Design Engineer

Marvell

Posted 2 days ago

VIEW JOBS 3/22/2019 12:00:00 AM 2019-06-20T00:00 Job Description Marvell is experiencing solid growth. Our newer business group with Machine Learning focus is hiring aggressively for key programs. This is an opportunity to: * Be a member of a design-team developing Marvell's machine learning chip. In this role, you'll help shape the micro-architecture of the chip working closely with the architecture team. You'll write specifications for the relevant block, develop micro-architecture of the block, and implement the design using RTL coding techniques, Synthesis, place and route, and timing signoff. * Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation plus debug. * Work with the physical design teams in aiding the implementation of the functional blocks. * Work with post silicon group to resolve any lab issues or customer issue Key Requirements * BSEE or equivalent required with up to 7+ years of experience in RTL design of submicron SOC products (eg: Microprocessor based SOC's). MSEE with 5+ years of experience. * Experience in Micro-architecture for the complex Custom/ASIC products focusing in any one/more areas: Embedded Processors, DSP, Graphics, and/or general purpose microprocessors. * RTL design experience, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification. * Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a plus. * Preferred/Optional: * Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus. * Experience in implementation/timing * Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell, etc. is desirable. Design automation experience is a plus as well. * Experience with SystemVerilog, UVM and Formal Verification (Jasper, VC-Formal, Questa-Formal) is a plus * Must have effective interpersonal, teamwork, and communication skills. * Excellent communication skills to interface internally and externally with all levels of the organization and to participate in problem solving and quality improvement activities. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Marvell Santa Clara CA

Sr. Staff Digital Design Engineer

Marvell