Sr Principal Design Engineer Soc Hardware

Cadence San Jose , CA 95111

Posted 8 months ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

You will be a member of the Central Applications Engineering team for Tensilica products at Cadence Design Systems, in San Jose, CA. You will focus on SoC hardware system design & verification using Tensilica processors. Members of the CAE team are technical experts in their field. In this position you will work with Tensilica development and customer support teams. You will develop examples, application notes, and training material. You will also help support customers and Field Application Engineers in designing and verifying their processor-based systems.

Responsibilities:

  • Become an expert on Tensilica processor RTL, interfaces, interconnects and memory subsystems.

  • Develop examples and best practices for SoC system hardware design, verification and testbenches for Tensilica processors.

  • Work closely with the customer support team to answer advanced questions on system design and verification. Interact directly with customers as needed to achieve this objective.

  • Develop customer training and help train customers and field application engineers on Tensilica processor architecture, interfaces, system verification, and hardware tool flow.

  • Write documentation, application notes, examples, and create and maintain a Knowledge Base on system design and verification.

  • Develop example system designs and use cases.

  • Complete evaluation and review of new products and features before release.

  • Provide feedback on customer usage of Tensilica processors and requests for enhancements so that future products may better serve customer requirements.

Required Skills:

  • Deep knowledge of SoC system architecture, interfaces, and interconnects.

  • Experience in SoC system simulation and verification.

  • Experience in SoC designs with caches, memory subsystems and DMA.

  • Familiar with on-chip bus protocols such as AMBA (AXI, AHB, APB), and on-chip trace and debug (JTAG, CoreSight).

  • Proficient in writing and debugging RTL (Verilog, System Verilog).

  • Experience in RTL design synthesis and timing analysis are a plus.

  • Strong communication skills written and oral are required.

  • Experience in working with customers and resolving customer issues, writing product documentation, and creating training material and presenting such material are strongly desired.

  • BS in EE/CS with 10+ years work experience or MS in EE/CS with 8+ years work experience required.

  • Some travel (up to 15% of time), including international travel is required.

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Sr Principal Design Engineer Soc Hardware

Cadence