Sr. Fpga Design Engineer (Contract)

Position : Contract

Length of position : up to 12 months.

Our Company

Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Recogni is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Recogni is a well funded, fast-paced startup company with headquarters in both San Jose, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.

About the role

To keep pace in this exciting, multi-disciplinary field, we're looking for a Sr. FPGA Design Engineer. You will be in a unique position to work in aspects of Recogni's next generation cutting-edge AI Hardware design. This will be a contract position that may last up to 12 months.

This hands-on role provides a unique opportunity to interact directly with ASIC, hardware design, software, product and operations teams to gather necessary requirements and specifications, and help come up with solutions to drive the product execution.

Responsibilities

• Design and implement FPGA-based prototypes to validate critical aspects of our planned hardware design.

• Lead the architecture definition, RTL block level programming, synthesis, and timing closure of a high speed Xilinx FPGA design used in validation of multimodal AI inference acceleration connectivity.

• Work with multi-functional teams (e.g. hardware, software, diagnostics and signal integrity engineers), and assist in complex subsystem level lab bring-up, integration, and unit test validation.

Desired Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related fields with 7+ years of experience years of proven, hands-on experience in FPGA prototyping.

• Strong Verilog HDL programming skills, with experience targeting RTL designed for custom ASIC Development to a Xilinx FPGA.

• Experience designing solutions that interface with Ethernet based protocols, PCIe, and optical transceivers, with knowledge of signal integrity and system bring-up

• Basic knowledge of UNIX OS, device drivers, and scripting tools

• Excellent verbal and written communication skills with a passion for technology innovation within a collaborative engineering environment.

• The candidate should be able to work independently and be comfortable in a fast-paced environment with tight deadlines.

Recogni is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

A note to Recruitment Agencies: Please don't reach out to Recogni employees or leaders about our roles -- we've got it covered. We don't accept unsolicited agency resumes and we are not responsible for any fees related to unsolicited resumes. Thank you for your understanding.