Sr. Engineer, Asic CAD

Sr. Engineer, ASIC CAD

Summary

The ASIC CAD Engineer is responsible for building and maintaining the ASIC design infrastructure, installing and maintaining the process design kits (PDKs) from foundries, and working with IT to install and configure the EDA tools used in designing our complex SoCs. You will work in a dynamic environment as part of a small IC design team. The ideal candidate is a hands-on self-starter who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.

Essential Functions:

• Build and maintain the design environment to support operation of the ASIC and AMS design teams.

• Install and maintain process design kits (PDKs) and IP libraries used in designing complex SoC's.

• Build and maintain regression testing infrastructure for the SoC design environment

• Install and configure EDA design tools from major vendors, such as Cadence, Siemens EDA (Mentor), Synopsys, in conjunction with IT

• Support the development of ASIC design flows and methodologies, including flows for synthesis and physical design.

Basic Qualifications:

• BS, MS in Electrical Engineering, Computer Engineering, or related fields.

• 2 to 5 years of work or academic experience in ASIC CAD.

• Familiarity with a Cadence Virtuoso design environment

• Familiarity with frontend and backend ASIC design processes and flows.

• Familiarity with PDKs and CAD/EDA tools for ASIC design and their interoperability.

• Proficient in version control software such as Git, Perforce, SVN, etc.

• Experience installing and configuring process design kits (PDKs) in advanced foundry processes (45nm and below).

• Knowledge of operating system shell scripting or other scripting languages, such as Python, PERL, and others.

• Knowledge of SKILL, Tcl/Tk, and Calibre DRC/LVS verification decks syntax.

Preferred Qualifications:

• Proficient in ASIC synthesis (Genus, Design Compiler), place-and-route (Innovus, ICC), and timing (Tempus, PrimeTime) / power (Voltus, Redhawk) sign-off tools.

• Proficient in continuous integration / continuous deployment (CI/CD) workflows

• Ability to execute analog and/or digital ASIC design flows for performing design tasks.

• Knowledge of back-end ASIC design elements, such as layout, physical verification, and design verification.

• Familiarity with cluster schedulers, such as Slurm, LSF, Kubernetes

Pay Range is $120K to $165K

Recruiters:

Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and please don't contact our managers or employees.

About Ayar Labs:

At Ayar Labs we're about to revolutionize computing by moving data with light. We're unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today's electrical I/O -- making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O. This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption.

With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work.

We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities.

Resources:

• Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video)

• Ayar Labs in the News and Recent announcements

• LinkedIn and Twitter

Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.