At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially talented DV Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every day.
As a Senior Verification Leader, the individual will manage a verification team collaborating with the engineering design team and developing the verification environment for new silicon developments. This is a technical, hands-on management role.
Lead the verification team, including taking responsibility for hiring, resource planning, scheduling, communication with upper management and overall verification team execution.
Take responsibility for performance management of individual team members including goals management, performance evaluations, promotions and disciplinary actions as required.
Take responsibility for all aspects of verification methodology employed by the team and ensure the application of uniform standards and adoption of best practices.
Work with other DV teams within Apple to identify holes in the design verification flow and implement corrective action.
Work closely with the design team to review specifications, understand chip architecture, develop tests & coverage plans, define methodology & test benches.
Typically requires at least 10+ years of industry experience. Prior verification team management experience is required. Prior experience verifying silicon ICs shipping in high volume is required. Advanced knowledge of ASIC design and verification flow including RTL design, simulation, synthesis, testbench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation Experience with low-level programming of systems in C/C++/assembly. Experienced with UVM. Specman is a plus. Knowledge of industry standard interfaces, deep understanding of Verilog, Verilog simulator and debug. Experienced in writing scripts in languages such as Perl, Python, and Tcl. Understanding of constrained random verification process, functional coverage, and code coverage. Experience with formal verification tools is a plus. Should be a great teammate with excellent interpersonal skills and the desire to take on diverse challenges.
Education & Experience
MS Degree or equivalent