Senior Staff Engineer/Principal Memory Design Engineer

MediaTek's advanced Memory Design team in San Jose is looking for a senior memory design engineer to define and architect memory circuits for high performance compute ASICs targeting Cloud AI, Data Center Networking, Automotive and other Enterprise ASIC applications as well as edge AI Machine Learning (ML) Accelerator SoCs • Primary job responsibilities include close collaboration with tier-1 ASIC customers in North America to co-design embedded memory architectures and circuits in advanced nodes • Collaborate closely with product and architecture teams to define, design, and develop high performance customized semiconductor memories including SRAM, TCAM, CPU caches and Compute-In-Memory (CIM) macros with varied PPA requirements spanning across Cloud AI, Networking, Automotive and edge AI applications • Design dual rail custom memories from start to finish to meet customer PPA spec Innovate, design, and incorporate special circuits and features to achieve best-in-class PPA for custom and compiler memories • Mentor, guide, and direct other designers, while being hands-on in digital circuit design, especially targeting memories • Highly organized and independent design engineer who can multi-task and closely collaborate with worldwide design and CAD teams Salary range: $180,000 - $260,000 Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications.

In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Paid time off (PTO), Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.

• 12+ years of hands-on experience in design of embedded memories (SRAM, TCAM) for high performance processors or ASICs in advanced nodes (3nm/5nm) • Strong track record of offering innovative solutions (papers, patents), good understanding of technology roadmap and market for embedded memories • Strong understanding of Digital Circuit design techniques in FinFET technologies • Exposure to complete design cycle of SRAM memory and compiler development • Supervise layout engineers and review layout for optimality • Have the ability to come up with comprehensive design verification plans, silicon bring-up plans for high-performance embedded memories • Experience with LEC tools (ESPCV) Ability to review and coordinate layout activities • Silicon debug and bring up experience is required • Working knowledge of scripting in Perl/Python • Willingness to collaborate closely with cross functional teams across the globe