Senior SoC Component Design Verification EngineerJob Description
The Programmable Solution Engineering group is responsible for High Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA emulation prototyping, validation and debugging.
As an IP Design Engineer focusing on IP Verification & Validation, you will be responsible for carrying out design validation for Intel next generation IP's across the Intel FPGA IP product portfolios. The charter of IP verification & validation team is to verify and validate the IP for robust functionality from functional simulation, FPGA emulation prototyping, to complex system level environment. The verification and validation areas encompass IP's for external memory interface protocols (eg. DRAM, SRAM) and high-speed transceiver protocols (eg. UPI - Preferred, Ethernet, Interlaken, PCIe, Serial Lite).
Create comprehensive verification and validation plan based on IP/FPGA architecture specifications and carry out all the IP validation tasks. The plan encompasses functional, system level and hardware verification and validation perspectives.
Developing IP/subsystem/system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. Writing directed and random test cases, debugging failures, filing and closing bugs.
Review verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics.
Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits.
Build IP FPGA emulation prototypes, creating and establishing IP subsystem/solution validation coverage strategy and standardized framework, drive system test design implementation and overall IP system validation on HW, maximize FPGA hardware capability to bring substantial improvement to IP quality & usability for Intel FPGA IP product portfolios.
Developing verification and validation tools and flows, as needed.
Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market
Bachelor's degree in Electrical Engineering, Computer Engineering or equivalent with at least 7 years of experience in verification, with a complete understanding of design verification flow
Experience in building block and system level test benches using System Verilog, UVM constrained random tests and latest verification methodologies.
UPI/Ethernet related verification experience is preferred.
Good debugging skills and working knowledge of scripting using Perl or Python
Experience in driving verification to closure by closing regressions, functional bugs and code and functional coverage.
Experience with IP architecture, development, verification, and rollout
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.