Senior Principal Design Engineer - Verification

Cadence San Jose , CA 95111

Posted 7 months ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is the leader in hardware emulation-acceleration technologies and products. Looking for an experienced ASIC and FPGA designer interested in challenging opportunities to develop complex and creative architectures and designer solutions to difficult problems. This position is located in our Belo Horizonte office, reports to the Sr. Design Engineering Manager, and works in a growing talented organization.

Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters. At the heart of these systems are a multitude of interconnected highly complex high-performance computing (HPC) devices based on a proprietary Boolean processor architecture. This is a role on the core technology team responsible for research and development of these ASIC engines and how they work as a system to reprogrammably emulate customers' logic circuitry up to multi-billion-gate systems. In this role, you will be responsible for developing and leading the development of major ASIC blocks and subsystems (in some cases involving FPGAs), from concept to productization including: balancing performance, area, power, and complexity, interfacing to third-party IP, working with physical design team on floorplanning and other physical issues, etc. Also, you will be needed to provide on-site leadership and management: guide, mentor, and motivate more junior engineers, track and report on ongoing design work, provide timely feedback and support for staff, help build the team through the interviewing and hiring process.

Requirements:

  • Bachelor's in Computer Science or Electrical Engineering + a minimum of 10 years of related experience; or Master's + 7 years of related experience; or PhD + 5 years of related experience.

  • Demonstrated capability to design major blocks involving ASIC, IPs, logic, and FPGAs.

  • Excellent logic developer in Verilog / SystemVerilog.

  • Relevant experience in some major IPs and protocols, such as SERDES, PCIe and DDR4, and ASIC IP integration in general. Expert in at least one such area.

  • Ability to work cross-functionally. Ability to quickly multi-task among many small projects.

  • Self-driven. Good communication, organization, analytical, presentation and people skills.

We're doing work that matters. Help us solve what others can't.


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Senior Principal Design Engineer - Verification

Cadence