Responsibilities: - Responsible for design, verification, implementation (ASIC) for high-performance, physical layer, high speed wired data communication networks including relevant signal processing algorithms.
Develop ASIC specification, architecture, and micro-architecture for major functional blocks in complex SOC solutions, for implementation signal processing and communications algorithms.
Development/simulation of RTL hardware implementations in VerilogHDL.
Synthesis, gate level simulation, timing analysis, design for test, Lab testing and debug for complex digital ASICs. #LI-KB1 #GLDR Requirements
4+ years plus experience in developing, implementing, and testing high performance communications and DSP ASIC products.
Extensive RTL experience including design, verification, synthesis and timing closure.
Strong UNIX-based EDA tool skills and in-depth knowledge of ASIC design flows.
Familiar with reusable HDL coding styles and design for high volume manufacture.
Familiar with signal processing circuit structure and architecture and high performance datapath arithmetic circuit design and optimization.
Familiar with C-shell, Perl script.
Experience in MATLAB and C/C++ based system simulation and evaluation a plus.
Familiarity with DSP and PHY layer communication protocols of 802.3 is a plus. Education: BSEE required; MSEE/PhD preferred.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.