Senior Fpga Design Engineer

THE OPPORTUNITY

Silvus is seeking a full-time Senior FPGA Design Engineer to join our Engineering Group, reporting to both the Senior Engineering Director for Irvine and the Director of FPGA Engineering (dotted-line). The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D. These are exciting projects targeted to address challenging real-world communication needs.

The Senior FPGA Design Engineer will be based at our new Silvus office, located in Irvine, CA. The position will be on a hybrid schedule, with a minimum of 4 days/week on-site (with the occasional drive to the Los Angeles HQ as needed).

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

• Digital design architecting for wireless communication projects.

• Fixed point design of signal processing blocks while working with systems engineers.

• RTL coding, simulation, and test bench development.

• FPGA synthesis and timing closure.

• Hardware verification and troubleshooting; familiarity with logic analyzers.

• Provide support to the RF and Software Engineering Teams.

REQUIRED QUALIFICATIONS

• Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields.

• Minimum 8 years of demonstrated experience in FPGA design; 4 years of FPGA design experience with an MS or advanced degree.

• Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.

• Proven expertise working with multiple clock-domain, high-utilization FPGA designs.

• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

• Master of Science degree in Electrical Engineering (MSEE).

• Basic MATLAB skill.

• Experience with communication systems on FPGA or ASIC designs.