At Palo Alto Networks everything starts and ends with our mission:
Being the cybersecurity partner of choice, protecting our digital way of life.
We have the vision of a world where each day is safer and more secure than the one before. These aren't easy goals to accomplish but we're not here for easy. We're here for better. We are a company built on the foundation of challenging and disrupting the way things are done, and we're looking for innovators who are as committed to shaping the future of cybersecurity as we are.
We are looking for a self-motivated, team-oriented, senior ASIC engineer to drive/lead critical aspects of the ASIC implementation and physical design effort. This individual will be a key member of the design team implementing complex digital ASICs used in next-generation firewall products. Responsibilities will include implementation, DFT, physical design and validation of the ASIC.
Responsibilities will include methodology definition and development as well as hands-on implementation for every aspect of ASIC implementation, DFT, and physical design; starting from RTL code to creating a physically realizable chip design and validation of the final implementation
Module and full chip level synthesis
Full chip netlist generation and floorplanning
Static timing constraint generation/analysis/closure
Package specification and planning
Work with the ASIC vendor and the design team to define and implement the DFT solution
Work with the ASIC vendor as well as the design team to optimize synthesis, timing closure, placement, routing, and validation of the ASIC
BS EE, CE or CS; or equivalent work experience required, MSEE preferred.
Minimum of 7 years of ASIC implementation and physical design experience required
Experience in going through several complete and successful ASIC design cycles from RTL to tape-out, including at least one as a physical design lead/manager required
Strong leadership/communication/interpersonal skills required
Experience with 28nm or smaller process technology required
Strong synthesis and static timing analysis skills required
Design automation, including strong scripting (Unix/TCL/Perl) and Makefile experience required
Experience with JTAG, IEEE1149.X standards, memory and logic BIST highly desirable
Networking ASIC experience is highly desirable
Our engineering team is at the core of our products connected directly to the mission of preventing cyberattacks. We are constantly innovating challenging the way we, and the industry, think about cybersecurity. Our engineers don't shy away from building products to solve problems no one has pursued before.
We define the industry, instead of waiting for directions. We need individuals who feel comfortable in ambiguity, excited by the prospect of a challenge, and empowered by the unknown risks facing our everyday lives that are only enabled by a secure digital environment.
We're trailblazers that dream big, take risks, and challenge cybersecurity's status quo. It's simple: we can't accomplish our mission without diverse teams innovating, together.
We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at email@example.com.
Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.
Palo Alto Networks Inc.