Senior Advanced ASIC / FPGA Engineer
Job ID: 2020-44085
Type: Full Time
General Dynamics Mission Systems
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 13,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas.
Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high performance team!
General Dynamics is an Equal Opportunity/Affirmative Action Employer that is committed to hiring a diverse and talented workforce. EOE/Disability/Veteran
Bachelor's degree in Electrical or Computer Engineering, a related specialized area or field is required (or equivalent experience) plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience.
Department of Defense Secret security clearance is preferred at time of hire. Applicants selected will be subject to a U.S.
Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
REPRESENTATIVE DUTIES AND TASKS:
Senior FPGA Design Engineers research, design, develop and test military electronic equipment and systems at GDMS including: avionics mission computers, stores management systems, signal and radar processing systems and related equipment.
The successful candidate will participate in a team environment to execute Requirement Decomposition, FPGA Digital Logic Design, Synthesis, Timing Analysis, Verification, and integration activities.
Responsible for requirement definition/clarification, design, verification, associated documentation for FPGA development, design revision control and archival.
Determines detailed design approach.
Defines FPGA interfaces and all aspects of device design and simulation.
Evaluates and tailors process flow including but not limited to high level design, synthesis, place and route, timing and power utilization for programs.
Creates test and verification plans that establish functional criteria to ensure requirements have been met.
Verifies test results against requirements and analyzes performance.
May provide leadership and/or direction to lower level employees.
KNOWLEDGE SKILLS AND ABILITIES:
Looking for an experienced FPGA digital logic Design Engineer. The position requires familiarity with a variety of digital logic design techniques including PWB, electronic module, and lab checkout.
This position requires a self-starter, able to translate customer requirements into a cost-effective design optimized for manufacturing and periodic operational maintenance. The candidate must be able to multitask and prioritize while dealing with several projects.
The candidate has decomposed statements of work into digital logic design requirements and used formal methodologies/tools to capture and track requirements
The candidate has successfully lead FPGA design or verification activities to ensure implementation and verification of all requirements
The candidate is familiar with high speed network switch design approaches
The successful candidate will participate in a team environment to execute FPGA Logic Design activities targeting Xilinx and/or Altera FPGAs, Synthesis, Timing closure, Verification and Lab FPGA integration
The candidate has Board and Module digital logic design experience and been a member of a successful integration team
The candidate has generated and executed constraint driven synthesis and timing closure techniques
The candidate is a Verilog expert and familiar with System Verilog
The candidate is familiar with VHDL
The candidate has used constrained random verification approaches
The candidate has experience designing high speed interfaces and complex memory designs
The candidate is familiar with embedded micro-processing systems
The candidate has design experience with protocols such as DDR, 10G Ethernet, Fibre Channel and PCIe in networking applications
The candidate has design experience integrating 3rd party IP
The candidate has expertise with various scripting languages and approaches
The candidate is proficient with Mentor Questa
At least 10 years of relevant work experience consisting of FPGA Verilog HDL Digital Logic Design techniques, methodologies, and related verification activities. Familiarity with digital signal processing and various digital video formats is a plus.
The candidate is very familiar with Gigabit network switches
The candidate has 1553
The candidate is familiar with GIT Lab and has Jenkins scripting experience
Familiarity with DO-254