RF Analog Mask Layout Designer - San Jose

Qualcomm San Jose , CA 95111

Posted 4 months ago

Job Detail

Job IdN1967087Job TitleRF Analog Mask Layout Designer

  • San JosePost Date10/02/2018Company-DivisionQualcomm Atheros Inc-Qualcomm Atheros

Job AreaEngineering Support

LocationCalifornia

  • San Jose
Job Overview Provide accurate schedules Meet project milestone deadlines Debug complex verification failures Proficiently use Cadence 6.1.6 and Calibre tools Deliver high quality layout that conforms to all design requirements. Contribute to hierarchical planning (top down and bottom up) and integration Work on 40nm, 28nm or 14nm FinFET circuits as team member in the Full Custom Layout environment." id="hdnJobOverview" />The Layout Designer will be responsible for physical design of RF and Analog circuits in a fast paced environment.

Responsibilities:

Provide accurate schedules Meet project milestone deadlines Debug complex verification failures Proficiently use Cadence 6.1.6 and Calibre tools Deliver high quality layout that conforms to all design requirements. Contribute to hierarchical planning (top down and bottom up) and integration Work on 40nm, 28nm or 14nm FinFET circuits as team member in the Full Custom Layout environment.All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.Minimum Qualifications Experience with 40nm, 28nm and 14nm FinFET processes

Proficiency with Cadence Virtuoso IC6.1.7 and IC12.3 (OpenAccess)

Proficiency with Calibre verifications tools.

Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, etc.

Full familiarity with Cadence Virtuoso IC6.1.7 and IC12.4 and Mentor Graphics Calibre tools
40nm, 28nm and 14nm FinFET design processes

Able to work in a team environment with other Mask Designers and Design Engineer's

" id="hdnMinimumQualifications" /> Experience with 40nm, 28nm and 14nm FinFET processes

Proficiency with Cadence Virtuoso IC6.1.7 and IC12.3 (OpenAccess)

Proficiency with Calibre verifications tools.

Custom layout experience must include high frequency circuits such as LNAs, Mixers, VCOs, etc.

Full familiarity with Cadence Virtuoso IC6.1.7 and IC12.4 and Mentor Graphics Calibre tools
40nm, 28nm and 14nm FinFET design processes

Able to work in a team environment with other Mask Designers and Design Engineer's

Preferred Qualifications 5 years of experience in RF/analog layout Design 3 to 5 years of 28nm and 14nm FinFET experiences Outstanding written and verbal communication Proficiency in the Full Custom RF Analog Layout Design environment " id="hdnPreferredQualifications" /> 5 years of experience in RF/analog layout Design 3 to 5 years of 28nm and 14nm FinFET experiences Outstanding written and verbal communication Proficiency in the Full Custom RF Analog Layout Design environment Education RequirementsRequired: Associate's or equivalent experience

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RF Analog Mask Layout Designer - San Jose

Qualcomm