Processor Performance Power Optimization

Cadence San Jose , CA 95111

Posted 3 months ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

R27649 Processor Performance Power Optimization


We are seeking candidates to join our Cadence/Tensilica IP architecture team to work on one of the most flexible architectures in the world. Our products and IPs span diverse markets including Machine Learning, Vision, Audio, and Networking.

Role and Responsibilities:

  • You will play a key role in building and enhancing our performance-power-area (PPA) model for our key products and IPs.

  • You will leverage your power analysis expertise and performance modeling knowledge to qualify power-performance tradeoffs of various design and architecture alternatives.

  • You will work closely with the design and CAD teams to understand and optimize implementation of different micro-architectural choices and their impact on frequency, power, and area.

  • You will help guide early products definition by providing alternative PPA design options for the product and marketing teams.


  • Master's degree in Electrical or Computer Engineering or related field.

  • 7+ years hands on experience in PPA analysis and optimization.

  • Very good knowledge of power-performance simulation and related infrastructure.

  • Very good understanding of micro-architecture choice impact on PPA.

  • Basic knowledge of physical design and power tools and flows is a plus.

  • Excellent scripting skills including Python, Perl, TCL, C/C++, and/or C-shell.

  • Strong communication skills as the role involves frequent interaction with members of the architecture, design and CAD teams.

We're doing work that matters. Help us solve what others can't.

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Processor Performance Power Optimization