Principal Verification Engineer, Vision BU

The Vision business unit is responsible for creating power-efficient System-on-a-Chip (SoC) ASIC devices for the automotive market.

Responsibilities

• Block and chip-level verification using the industry standard UVM methodology

• Verification plan and methodology

• Test bench infrastructure development

• Creation of random and constrained random test cases

• Specification and collection of functional & code coverage

• Support FPGA emulation team with test case debug

• Interaction with the post-silicon validation team for ASIC bring-up and characterization

Requirements

• Bachelor's degree in Electrical/Computer Engineer (Master's preferred)

• 10+ years of complete lifecycle experience with multiple ASICs

• Familiarity with verification of System-on-Chip devices with embedded processors,

• Progressive hands-on experience building UVM test benches and test sequences

• Solid understanding of SoC protocols such as AMBA, DDR memory, MIPI, I2C, SPI, UART etc.

• Solid understanding of random and constrained random testing using UVM methodology

• Proactive approach to design debug and problem solving

• Good written and verbal communication skills

Demonstrated, progressive hands-on experience with industry standard verification tools, specifications, protocols, and Verification IP is a basic requirement of this position. Familiarity with power intent verification (UPF), design prototyping on FPGAs, and emulation systems such as HAPS & Zebu are especially attractive.