Infinera is the global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine network. Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world's largest and most demanding networks that generate billions in service revenue for our customers.
Principal SerDes Systems HW Engineer
Location: Position available for both San Jose, California and Allentown, PA.
This person will be an integral member of a focused SerDes/SI Systems HW team that will be slated to validate and test the latest Infinera ASIC products which include high speed SerDes to be used in Infinera's state of the art optical systems.
Responsible for post-silicon validation, troubleshoot and debug of high speed SerDes in the ASICs
Responsible for PVT characterization of high speed SerDes test-chips and production ASIC's
Evaluation and selection of SerDes PHY topologies, transmitter and receiver capabilities, equalization tuning, and related clocking / power supply considerations to meet critical performance and robustness objectives
Create SerDes validation plans, write and execute test cases; creatively debug lab issues and drive to solutions
Perform circuit simulation / correlation to lab data, and methodical characterization of SerDes circuits
Work with and drive suppliers to optimize tuning parameters and perform root cause/corrective action of defects and under-performing links. Suppliers would include both external vendors and internal (INFN ASICs)
Drive SerDes technical solutions across functional product development teams in PIC module, ASIC, firmware, mechanical, and test software. Needs good communication skills and ability to analyze/present data and determine/drive next steps
7+ years of experience of high speed PCB design, and/or high speed SerDes silicon validation
Strong Hardware design knowledge and familiarity with high speed PCB layout, signal integrity (T-line, crosstalk, Power Distribution Networks)
Knowledgeable in SerDes signaling (PHY layer) such as 56G PAM-4
Fundamental understanding of circuit theory, linear system theory, electronic noise suppression, transmission line, communication and signal-processing theory
Background in analog/mixed-signal integrated circuit design, and developing integrated analog circuits for SerDes, CDRs, and PLL/DLLs will be an added plus
Comprehension of current high-speed communication standards such as IEEE 400GUAI-8, CEI-28G/56G.
Experience in post-silicon validation, troubleshooting and debug SerDes design and debug experience, understanding of transmitter and receiver equalization, CDR behaviors, modeling, and link training algorithms
Proficiency with one or more engineering tools like Matlab, ADS, Ansys SIwave.
Requires experience using high speed test equipment including Scopes, BERTs, Spectrum Analyzers
Track record of successful -validation of leading edge analog IP/production ASICs across multiple generations of product/technology
Software skills must include C/C++ and Python
Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/Disabled.