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Principal Engineer, Timing & Power Signoff

Expired Job

Cadence San Jose , CA 95111

Posted 4 months ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is the leader in hardware emulation-prototyping technologies and products. Looking for an experienced well-accomplished Principal Signoff Engineer interested in challenging opportunities to be a technical verification lead in verification of complex high-performance emulation processing ASICs and FPGAs, establish and implement advanced Timing and Power signoff methodologies and flows. This position is located in our San Jose headquarter office, reports to the Manager of R&D, and works in a growing talented organization.

Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters. At the heart of these systems are a multitude of interconnected highly complex high-performance computing (HPC) units based on a proprietary innovative processor architecture. This position is a critical role in the development of such system products, responsible for the verification of ASICs and FPGAs.

Key responsibilities

  • Assume the Technical Leadership role in a STA, IR-Drop.

  • Setup the Timing, & Power signoff methodology, tools and flows

  • Development of SDC's, Block level budgeting.

  • Develop and manage the Glitch Flow.

  • Ensure Block level and Top Level STA flows.

  • Develop and maintain Power Recovery methodology.

Qualifications

  • 10+ years of relevant experience. Degree in Electrical or Computer Engineering, graduate level or compensating experience.

  • Fluent in TCL & PERL.

  • Sound working experience with ASIC handoff

  • Fluent in Timing closure & STA Timing Flows.

  • Understanding of Power Signoff including IR-Drop & EM

  • Working knowledge of SDC, Verilog and CPF.P

  • Prior Physical design experience.cripting experience in PERL, Python, and Shell required, C/C++ preferred.

  • Synthesis flow expertise required.

  • Demonstrated technical abilities and capable of leading and solving technical challenges. Ability to work cross-functionally.

  • Energetic. Self-driven. Good communication, organization, analytical, people, project planning, and leadership skills.

  • Proven success in development of complex custom ASIC products in advanced process nodes preferably FINFET technologies

We're doing work that matters. Help us solve what others can't.


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Principal Engineer, Timing & Power Signoff

Expired Job

Cadence