Principal Engineer - Physical Design

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Job Description:

To support Physical Design-related project activities for the multiple 32-bit Business Units in Microchip.

The product's focus is on microprocessors, microcontrollers, and wireless design and implementation.

• Implement all aspects of physical design, such as floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance, and physical verification.

• Perform all aspects of Chip Power Integrity for multiple voltage domains, such as IR drop analysis, signal & Power EM, and cross talk analysis.

• Utilize hierarchical systems-level design techniques to build designs exceeding multimillion gates.

• Working on the place and route methodologies and low power methodologies.

• Must be a self-motivated team player who can collaborate with multiple teams across a geographically diverse company to achieve desired design goals.

Detailed job functions include:

• Timing closure support to maximize process node capability.

• Clock tree setup/debug and synthesis for optimal QoR.

• General physical implementation procedures.

• Multi-voltage island-based floorplan design and support.

• Flow development and automation implementation.

• Delivering Physical Verification-clean designs.

• Die size estimation and Bond out approval.

• Interfacing with external vendors and IP sources to resolve problems.

• Working with members from international design/implementation teams.

Requirements/Qualifications:

The successful candidate will have a Masters with 7 years or more applicable technical experience in the physical and timing-related aspects of IC design, or a Bachelors with 10 years of experience. The design task requires experience in the following Physical Design- related activities:

• Advanced knowledge of VLSI logic principles, Power integrity and reliability (EM & IR) analysis.

• Advanced knowledge of place and route methodologies and low power methodologies.

• Knowledge of clock tree synthesis & debug, and design timing closure.

• Experience with 28nm or lower technologies

• Detailed systems-level floorplanning.

• Power network planning.

• Multi-voltage/low power implementation techniques.

• Detailed knowledge of ICC/ICC2 or Innovus and Redhawk toolsets.

• Proficiency in Tcl and Perl scripting is essential.

• Excellent debugging and analytical skills.

• Good verbal and written communication skills and strong interpersonal skill

Travel Time:

0% - 25%

Physical Attributes:

Hearing, Seeing, Talking

Physical Requirements:

80% sitting, 10% walking, 10% standing

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.