Principal Digital IC Design Engineer - Machine Learning

Marvell Santa Clara , CA 95051

Posted 1 week ago

Marvell is looking for a Principal level engineer to join our machine learning team. In this role you will define / architect complex Custom/ASIC products focusing on Embedded Processors, DSP, Graphics, and/or general purpose microprocessors. We need an expert in the areas of RTL design, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification.

  • Must have effective interpersonal, teamwork, and communication skills.

  • Excellent communication skills to interface internally and externally with all levels of the organization and to participate in problem solving and quality improvement activities.

  • Demonstrates good analysis and problem-solving skills.

  • Has an inherent sense of urgency and accountability.

  • Must demonstrate initiative and a bias for thoughtful action.

  • Grounded, detail-oriented, always backs up ideas with facts.

  • Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

  • Must have the ability to multi-task in a fast paced environment.

  • Must have:

  • MSEE or equivalent required with 7+ years of experience in RTL design of submicron SOC products (eg: Microprocessor based SOC's).

  • Experience in Micro-architecture for the complex Custom/ASIC products focusing in any one/more areas: Embedded Processors, DSP, Graphics, and/or general purpose microprocessors.

  • RTL design experience, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification.

  • Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a plus.

  • Preferred/Optional:

  • Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus.

  • Experience in implementation/timing

  • Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell, etc. is desirable. Design automation experience is a plus as well.

  • Experience with SystemVerilog, UVM and Formal Verification (Jasper, VC-Formal, Questa-Formal) is a plus

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.


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