Principal Asic Design Engineer (1949-167)

Maxlinear Carlsbad , CA 92008

Posted 3 weeks ago

MaxLinear is seeking a talented and driven Principal ASIC Design Engineer to join our high-performing SoC team in either our Irvine, CA design center or our Carlsbad, CA design center and corporate headquarters. The building blocks in the SoCs we develop include DSP functions, CPU subsystems, packet processing engines, and high-speed interfaces. This role focuses on the following:

  • Responsible for the architecture, design, integration, and verification of communications/digital signal processing (DSP) SoCs

  • Work with communications systems engineering and product marketing to close design specifications, define block/core/chip architectures and HW/SW partitioning, carry out and verify the design

  • Mentor junior designers

Required Skills

  • ASIC design background with hands-on experience in RTL and verification, in-depth knowledge of mixed-signal SoC development cycle and best industry practices, from specification through tape-out and lab validation

  • Proven track record of success in high-performance/high-volume semiconductor markets

  • SoC, embedded CPU and bus architectures, networking and control interfaces

  • Communications/DSP and packet processing algorithms, and efficient implementations

  • Digital IC design, design for low power and high speed, design for test (DFT)

  • System modeling, RTL coding, Lint/CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence/Synopsys design environments

  • Verilog/System Verilog, C, and scripting languages

  • Embedded systems FPGA emulation, lab debug and silicon performance validation

  • Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets

  • Self-motivated, excellent communication skills and ability to excel and to provide leadership in a team environment

  • MS + 8 years of experience, or Ph.D.

  • 5 years of experience

Company Overview

MaxLinear is a global, New York Stock Exchange-traded company (NYSE: MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, designing highly integrated, radio-frequency, and mixed-signal Communications ICs for broadband and infrastructure applications.

We hire the best people in the world and engage them in some of the most exciting opportunities in our broadband and infrastructure markets. Our growth has come from innovative, bold approaches to solving some of the world's most challenging communication technology problems.

MaxLinear began by developing the World's first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn't achieve the extremely high performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we've developed a full line of products for satellite communications, cable modems, and terrestrial TV; diversified into high speed products addressing Datacom applications such as 400 Gbps fiber-optic interconnect chips for high-speed networks; and MoCA technology for home networking.

Our headquarters is in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, CA; in Vancouver, Canada; in Valencia, Spain; and in Bangalore, India.

We have approximately 800 employees, a substantial majority of whom have engineering degrees, and include masters and Ph.D. graduates from many of the premiere universities around the world. Our engineers thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building great products.

  • MON

Job Location Carlsbad, California, United States Position Type Full-Time/Regular


icon no score

See how you match
to the job

Find your dream job anywhere
with the LiveCareer app.
Mobile App Icon
Download the
LiveCareer app and find
your dream job anywhere
App Store Icon Google Play Icon

Boost your job search productivity with our
free Chrome Extension!

lc_apply_tool GET EXTENSION

Similar Jobs

Want to see jobs matched to your resume? Upload One Now! Remove
Electrical Engineer Analog/Digital Circuit Design (Ts/Sci Clearance)


Posted 2 days ago

VIEW JOBS 9/16/2020 12:00:00 AM 2020-12-15T00:00 Description: Job Title: Electrical Engineer - Analog/Digital Circuit Design (TS/SCI Clearance) Job Code: SAS20200907-47585 Job Location: Carlsbad, CA Job Description: Candidate will perform analog and digital circuit design using the Ansoft and Cadence tools. This includes schematic capture, bill of materials, component symbol and footprint design, collaboration with the Printed Circuit Designer to layout the board, CCA fabrication and population, then integration and testing the circuit through verification in the lab. Essential Functions: * Thorough knowledge of using the Cadence ConceptHDL and Ansoft tools to produce analog and digital circuits. This includes component selection, and simulation of the analog circuit performance * Perform BOM scrubbing for obsolescence, MTBF (Mean Time Before Failure) lifetime analysis, and component checks * Assist in component procurement and quality documentation processes * Manage local part libraries and assist stockroom with pull requests * Create the review package and present the circuit design at peer reviews. This includes analysis, performance budgets, and tests that demonstrate how the circuit will meet the requirements * Create a test plan and a test procedure to validate the circuit implementation meets the requirements Qualifications: * Bachelors Degree with at least 4 years of relevant experience OR a Graduate Degree with a minimum of 2 years of relevant experience. * Experience in analog and digital circuit design * Design experience through the development cycle including integration and test of a circuit design * TS/SCI security clearance Preferred Additional Skills: * Bachelor Degree in Electrical Engineering * Experience with high speed memory (DDR3/4), network (10/100/1000 ethernet) interfaces and telecom protocols (SONET/SDH) * Simulation experience with Ansoft SiWave is a plus * Layout experience using Cadence Allegro is a plus * Experience with Agile data management services is a plus L3harris Carlsbad CA

Principal Asic Design Engineer (1949-167)