Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.
The Serdes architect will be responsible to oversee PHY, PCS and controller logic architecture
Development of extremely high-speed communications transceivers integrated into high performance low power FPGAs
Candidate will have responsibility for defining partitioning of all the serdes subsystems and logic versus analog circuits, clocking and interfaces. The architect will be responsible for the system interfaces and interaction with subsystem, controllers and SOCs. Responsibilities will include participation in cross functional meetings and discussions for integration of Serdes blocks into the FPGA
Job opening also includes in helping guide the selection and specification of transceiver components using mathematical and computer modelling techniques. The candidate will collaborate with analog designers, digital designers, applications engineers, and marketing specialists to help guide tradeoffs among conflicting design goals, and as such will be responsible for the performance of the end-to-end system. This will also require bringup, testing, debug and characterization in lab and establish correlation between silicon and simlations. The position is full-time in our San Jose office.
MS EE/CE with 7+ years of digital FPGA design and validation experience
Knowledge of FPGA architectures is a must
Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
Strong technical background in FPGA prototype emulation, and debug
Strong technical background in silicon validation and debug
Board level debug capabilities in lab environment : hands-on troubleshooting skills for digital logic and analog circuit on PCB's using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)
Design with RTL coding in Verilog and VHDL is a plus
Hands-on systems level design and debug experience with embedded processors on FPGAs is a plus
Good understanding of SerDes architecture, including CDR, jitter tolerance, jitter generation, CTLE and/or DFE equalization, adaptation algorithms, high speed clocking, Signal and Power Integrity
Knowledge and experience in Serdes Protocols
Knowledge of PHY, PCS and controllers
Deep knowledge of communication systems fundamentals
Strong coding skills for simulation and modelling, as well as data analysis
Good experimental skills
Good knowledge of signal processing (DSP) algorithms and architecture
Good working knowledge of physics of signal propagation
Good working knowledge of basic circuits
Equal Opportunity Employer
Microchip is an Equal Opportunity/Affirmative Action Employer of Disabled / Veterans / Minorities / Women. We provide equal employment and affirmative action opportunities to applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other basis protected under applicable federal, state or local laws.
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Microchip Technology Incorporated