Computer Task Group is seeking a Physical Designer to work a long-term contract in either San Jose, CA, Austin, TX or Yorktown Heights, NY.
U.S Government Customer, has a need for an experienced physical implementation engineer. This engineer will assist in the development, implementation and testing of a digital neuromorphic accelerator chip. The selected candidate will work directly with other designers and system architects to implement ASIC physical design.
Synthesis and placement-driven synthesis
DFT and DFM implementation
In-depth understanding of memory structures
Physical design, including power grids, clock network implementation, floorplaning, place and route
Simulation and debugging
Timing closure and signoff
Power optimization and signoff
Extensive Scripting / Flow Automation
Basic Skills, clearances and other elements required, in order of importance, and number of years experience, where applicable, in each skill:
Other Skills Desired, Years in each skill, where applicable:
At least 4 year experience in multiple of the following categories: Place and route, Timing closure, Power optimization, DFT.
At least 2 year experience in scripting: Tcl and Python required.
Please send resumes to Tana.Stilloe@ctg.com or apply below.
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