Sorry, this job is no longer accepting applications. See below for more jobs that match what you’re looking for!

Physical Design Verification Engineer

Expired Job

Apple Inc. Santa Clara , CA 95051

Posted 3 months ago

Job Summary

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail?

As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.

Key Qualifications
5-10 years of physical design experience, with emphasis on physical verification Strong knowledge of physical verification flows and methodology

Deep knowledge of all aspects of ASIC physical design

Scripting skills to debug flow related issues and make improvements as appropriate

Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc

Real chip tapeout experience with a track record of successful signoff

Layout design background and experience a plus

Description

As a member of the physical design team, you will be responsible for:- Performing various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level- Working closely with the CAD/Technology teams for flow bring up and validation- Collaborating with the Implementation team during the entire chip design cycle to drive signoff closure for tapeout- Owning schedules and supporting cross-functional engineering effort- Work on padring, bump, RDL design collaborating with the package and floorplan teams

Education

BSEE or MSEE



See if you are a match!

See how well your resume matches up to this job - upload your resume now.

Find your dream job anywhere
with the LiveCareer app.
Download the
LiveCareer app and find
your dream job anywhere
lc_ad

Boost your job search productivity with our
free Chrome Extension!

lc_apply_tool GET EXTENSION

Similar Jobs

Want to see jobs matched to your resume? Upload One Now! Remove
Design Verification Engineer

Redolent, Inc

Posted Yesterday

VIEW JOBS 11/17/2018 12:00:00 AM 2019-02-15T00:00 We have the following urgent requirement with our client:<br />  <br /> Title:  <strong>Design Verification Engineer</strong><br /> Location: Santa Clara, CA<br /> Duration: <strong> 6+ Months</strong><br /> Compensation:  DOE<br /> <br /> <strong>Details</strong><br /> • Requires strong experience with development of<strong> UVM, OVM, VMM and/or Verilog, SystemVerilog t</strong>est benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.<br /> • Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.<br /> • Verification experience AXI, NoC, HBM, DDR4, PCIe verification is a plus.<br /> • Verification experience in full chip verification is a plus.<br /> • Strong understanding of different phases of ASIC and/or full custom chip development is required.<br /> • Experience in modeling SystemC and using SystemC based models in verification is a plus.<br /> • Experience with FPGA programming and software is a plus.<br /> • Verification experience in  PCIe, Processors, Graphics is a plus.<br /> • Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.<br /> • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.<br /> • Some DFX/DFT and UPF/power-aware-simulation experience is a plus Redolent, Inc Santa Clara CA

Physical Design Verification Engineer

Expired Job

Apple Inc.