Physical Design Engineers- San Diego Or Santa Clara

Qualcomm San Diego , CA 92140

Posted 2 months ago

Job Detail

Job Id E1973732 Job Title Physical Design Engineers- San Diego or Santa Clara Post Date 06/13/2019 Company Qualcomm Technologies, Inc.

Job Area Engineering

  • Hardware

Location California

  • San Diego

Job Overview QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.

You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification.

The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications Bachelor's degree in Science, Engineering, or related field. " id="hdnMinimumQualifications" />Bachelor's degree in Science, Engineering, or related field. Preferred Qualifications 2+ years industry experience/coursework in the following areas:

Physical Design Place & Route tool experience on Cadence Innovus and/or Synopsys ICC2 Timing closure experience in Synopsys PTSI Formal verification experience Physical verification experience" id="hdnPreferredQualifications" />2+ years industry experience/coursework in the following areas:

Physical Design Place & Route tool experience on Cadence Innovus and/or Synopsys ICC2 Timing closure experience in Synopsys PTSI Formal verification experience Physical verification experience Education Requirements Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering" id="hdnEducationalRequirements" />Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering

Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering Keywords



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Physical Design Engineers- San Diego Or Santa Clara

Qualcomm