We are now looking for a New College Grad for Physical Design/Timing Engineer.
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to tackle, which we love to work on, and that matter to the world. This is our life's work, to amplify human creativity and intelligence.
The Physical Design team is seeking a Timing Engineer to join their growing and dynamic team. You will be responsible for all aspects of physical design and implementation of Graphics processors, SOCs, integrated chipsets, and other ASICs. Make the choice to join us today!
What you will be doing:
Responsible for many different aspects of static timing analysis and closure on some of the most complex and challenging integrated circuits being built today. This can include constraint creation and validation, critical path analysis, timing ECO generation, and timing sign-off.
You may have the opportunity to tackle related physical tasks such as synthesis, equivalence checking, netlist generation, power and noise analysis, CDC, and functional ECO creation.
May engage with EDA vendors like Synopsys, Cadence, Mentor, etc. for tool suites such as: Physical Compiler, PrimeTime, dc_shell, Formality, and SPICE.
Have an opportunity to interact with a diverse team engineers across different chip functions.
Contribute your ideas and experience to help improve our overall methodology and approaches to timing closure (flow and tools development).
What we need to see:
You are pursuing a BS, MS or PhD in Electrical or Computer Engineering with a minimum GPA of 3.5
Demonstrate a deep understanding of Logic synthesis, equivalence checking/Formality, static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, placement, routing, circuit design and analysis, crosstalk delay, noise glitch.
You have scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, and Make.
It is a plus if you have previous internship or work experience in physical design implementation, methodology and/or flow development and automation.
Hands-on experience in industry standard EDA tools preferred. Familiarity of Synopsys PrimeTime is also a plus.
NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer with a real passion for computer architecture? If so, we want to hear from you!
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression , sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.