Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a Physical Design Engineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced technology nodes. You will perform technical evaluations of vendors, process nodes and IP and will provide recommendations. You will work with teams to understand and implement their requirements and drive block and full-chip level physical implementation and quality of results (power, timing, area). You will develop physical design methodologies, automation scripts and write documentation.
BS degree in Electrical Engineering or equivalent practical experience.
7 years of experience in ASIC physical design flows and methodologies in advanced nodes. Multiple foundry experience.
Scripting experience in Python, TCL or Perl.
Experience with ASIC physical design flows and methodologies including synthesis, place and route, STA, formal verification, CDC and power analysis.
MS degree in Electrical Engineering.
Experience solving physical design challenges across various technologies such as embedded processors, DDR, networking fabrics, etc.
Experience in extraction of design parameters, QOR metrics, and analyzing trends
Experience leading one or more aspects of physical design and IP integration (memories, IO's and Analog IP).
Working knowledge of semiconductor device physics and transistor characteristics and working knowledge of Verilog/System Verilog.
Perform block level physical implementation steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification.
Work with logic designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure.
Perform technical evaluations of vendors, process nodes, IP and provide recommendations.
Develop physical design methodologies and automation scripts for various implementation steps.