Mems/Analog IC Layout Design Engineer (Semiconductor)
Chandler , AZ 85224
Posted 3 weeks ago
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Westerwood Global (WG) a leading provider of manufacturing and technical support services exclusive to the semiconductor industry. At Westerwood Global, we work with our customers to provide Whole Fab support across all tool types.
Westerwood Global is a dynamic and growing company. We pride ourselves on offering industry leading, project & permanent, employment opportunities. Our employees are at the core of our service offering and their professional development is a vital aspect of the WG culture.
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The MEMS Layout Design Engineer will lead the Layout activities required for the development of new MEMS for Sensor Automotive. Candidates must have expertise on the following:
- Product floor planning, physical layout and verification (DRC, LVS and XOR checks), parasitic extraction, in new products and modifications to existing products
- Layout design and implementation following best practices from the industry
- Own layout design for multiple tape outs of MEMS devices, and test structures
- Delivery of layouts that are error free and DRC clean and on schedule
- Implementation of the MEMS design Layout requirements with efficiency and accuracy using industry standard design flows
- Parameterized layout, LVS, DRC and DFX
- Able to work across different teams to deliver layouts that are first time right.
- Responsible for Layout Design Review presentations.
- This position has responsibility for working directly with MEMS design engineers to create effective MEMS physical layouts.
- Work well in a Team environment and provide support to the MEMS Design Team.
- Minimum of BSEE or BSME and 4 to 6 years of experience in MEMS or Analog Layout Design.
- Demonstrated experience with MEMS or analog layout for silicon chips in mass production.
- Ability to estimate layout schedule for a given design, layout planning and provide early feedback to MEMS design engineers.
- Thorough knowledge of industry standard EDA tools from Cadence. Implement all aspects of the MEMS or Analog IC layout using Cadence Virtuoso. Must be able to set up LVS and DRC environments and debug verification issues using Cadence tools.
- Knowledge of layout extractions and techniques for device matching, minimizing parasitic, and routing.
- Ability to resolve LVS/DRC errors in a timely manner. Complete layout on time or ahead of schedule with quality.
- Ability to work and communicate effectively with MEMS designers (some located remotely) to understand the layout requirements.
- Must possess strong written and verbal communication skills
- Enovia dPDM knowledge a big plus.
- MEMS, Mechanical Design or background knowledge is desired.
Excellent Salary, Medical, Dental, Vision, Paid Vacation and Select Holidays, Overtime Opportunities, Compressed Work Week, On-site Facilities, Career Development Opportunities