Memory Cache Design Verification Engineer

Apple Inc. Austin , TX 78719

Posted 2 months ago

Does making the next great technology product excite you? Imagine what you could do here! At Apple, our new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish. The SoC Performance Verification is a critical job within Apple's Hardware Technology. Join this group and be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices.

Key Qualifications

  • Skilled in aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.

  • Knowledge of Verilog/System Verilog, digital simulation and debug.

  • Knowledge of memory architecture, coherency and digital design fundamentals.

  • Ability to work independently to deliver the project goals.

  • Exposure to UVM is desired.

  • Experience with C/C++ is a plus.

  • Experience with Perl, Python or similar scripting language.

  • Excellent interpersonal skills.


As part of a very hardworking team you will be at the heart of the chip design effort collaborating with all fields (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & test benches. It's required that you communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results.

Are you ready to join the team and immerse yourself in technology of the future? Apply today.

Education & Experience

BSEE or BSCS required, Master's or PhD desired.

icon no score

See how you match
to the job

Find your dream job anywhere
with the LiveCareer app.
Mobile App Icon
Download the
LiveCareer app and find
your dream job anywhere
App Store Icon Google Play Icon

Boost your job search productivity with our
free Chrome Extension!

lc_apply_tool GET EXTENSION

Similar Jobs

Want to see jobs matched to your resume? Upload One Now! Remove
Contract Design Verification Engineer

Samsung Electronics America Inc

Posted 3 days ago

VIEW JOBS 5/31/2020 12:00:00 AM 2020-08-29T00:00 Position Summary Samsung is a world leader in Memory, LCD and System LSI technologies. We are currently looking for exceptional software and hardware talent to join our Samsung Austin R & D Center (SARC) in Austin, TX and our Advanced Computing Lab (ACL) in San Jose, CA. SARC was established in Austin, TX in 2010 to be one of Samsung's strategic investments in high performance low power ARM based device technology. Presently our GPU design teams, located in Austin (SARC) and San Jose (ACL), are developing a GPU that will be deployed in Samsung mobile products. Our System IP team located in Austin (SARC) is working on Coherent Interconnect and memory controller architectures. As a Contract Design Verification Engineer you will contribute to the functional verification of GPU IP. This is a hands on role, driving next generation product development with a high level of contribution and knowledge base needs. Role and Responsibilities Key responsibilities include: * Review architecture specifications * Identify design features for verification and functional coverage * Develop verification/test plans and functional coverage plans * Work with RTL to create verification reference models and constrained random stimulus generators * Develop and maintain System Verilog/UVM test benches * Drive to coverage and verification closure * Manage tasks and deliverables to meet milestones Skills and Qualifications Minimum requirements: * BSEE, Computer Engineer or comparable and 5+ years of experience * Advanced knowledge on CPU and/or GPU design architecture * Basic RTL skills - can read and understand RTL design * Experience in verification tools System Verilog, UVM, and Verdi * Proficiency in scripting languages (TCL/Python) * Excellent communication skills and be able to work with cross-functional teams to execute verification plan Preferred candidate will possess the following: * Strong capability to read high level design specification and RTL to create/execute verification plans. * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here. Samsung Electronics America Inc Austin TX

Memory Cache Design Verification Engineer

Apple Inc.