Lead Digital Design Verification Engineer - UVM (76931)

Job Title: ASIC/FPGA Verification Engineer - UVM Job Location:

Cambridge MA 02139 (remote work is available) Onsite Requirements: UVM System Verilog FPGA/ASIC Job Description: The Client is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs.

In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation, and communications. You will develop verification approaches, author, and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects.

Join us as we develop the next generation of digital and embedded hardware platforms. Required Qualifications: BS degree with 8 years' experience Must have Lead experience.

Fluent in System Verilog including SVA. Recent experience with UVM Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS) Firm grasp of constrained-random and coverage-driven verification Experience with formal analysis. Practice using Python, Perl, Bash, or other scripting languages.

Ability to work in a Linux environment. Strong analysis and problem-solving skills Preferred Qualifications: Experience leading verification teams.

Experience with analog or mixed-signal simulations (AMS) 3rd party and subcontract staffing agencies are not eligible for partnership on this position. 3rd party subcontractors need not apply. This position requires candidates to be eligible to work in the United States, directly for an employer, without sponsorship now or anytime in the future. This client is a US Federal Government contractor and is legally required to hire US Citizens. US Citizens will only be considered for this role