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DFT senior position, responsible for all aspects of advanced DFT implementations in both chip-level and block-level. This will involve improvements in the DFT automation infrastructure, detailed understanding of DFT hardware, ATPG process, scan compression, MBIST, STA constraints for various DFT modes, independent problem solving debugging various simulation failures, formal verification, TCL knowledge, Perl knowledge, etc. Good understanding of testers, silicon debug. Deep familiar with low power scan/ATPG, memory BIST, memory repair, JTAG and boundary scan, AC-JTAG.
DFT flow maintaining and automation infrastructure development
Chip Design-for-Test implementation in both top-level and block-level
DFT design verification
ATE pattern generation, silicon bring-up and debugging
Strong knowledge on digital design and DFT methodology
Detailed understanding on DFT hardware, ATPG process, scan compression, MBIST, memory repair, boundary-scan test
Good understanding on STA constraints for various DFT modes
Good knowledge on JTAG, iJTAG, ACJTAG
Experience with industry standard EDA tools
Good understanding on testers, and silicon debug
Strong analytical and problem solving skills
In-depth knowledge on low power design
Good Knowledge in languages relevant to the ASIC development process including Verilog, TCL, Perl Scripting
Self-motivated, excellent communication skills and ability to excel in a team environment
Good organization skills, able to follow through & bring issue to closure
Understand the entire IC development flow & procedure including silicon volume production qualification requirements & procedures
Enthusiastic & enjoy IC development works
Be able to work with teams at remote locations with different time zone
Developing DFT solutions for the projects
Implementing SCAN, MBIST, JTAG in SOC designs for both block-level and top-level. Ensure to meet required tapeout goals.
Developing common DFT flow and methodologies commonly used in our department
Verification for all DFT related logic, including timing closure and pattern simulation for all DFT modes
Generating and validating ATE test patterns and support silicon bring-up and failure analysis
BSEE with minimum 12 years of work experience with direct related technical skill
Or, MSEE degree with 10+ years of work experience
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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