About the Position:
Signal Integrity Engineer working on system design with 56G and 112G PAM4 high speed serdes
Contribute in a team-oriented centralized SI organization performing system signal integrity design with exposure to new and different cuting edge technologies
Perform analysis and design and understand tradeoffs in designing interconnect solutions ranging from chip to chip, board to board, backplane and chassis to chassis interconnects.
Perform channel margin analysis to provide design tradeoffs amongst package, board, connector. Develop SerDes channel simulation models and correlate to test structures. Correlate Tx and Rx SerDes simulation models with measurements and work with SerDes vendors to improve model accuracy.
Perform PCB timing analysis, work with board engineers and layout designers to implement all SI rules, develop layout/SI checklists. Document SI rules.
Perform SI DVT measurements on boards and correlate simulations with DVT measurements.
Provide technical assessment of projects to SI management team.
Time Domain Reflectometers, Spectrum Analyzers, phase noise analyzers.
Good lab debug skills a plus.
geography in a matrixed organization. Leverage designs from other SI engineers
and share in learning of new designs with SI team.
Capable of presenting new work/concepts/analysis to SI team forums.
Proficient with CAD tools Ansys HFSS, ADS, SPICE, Matlab, Cadence Allegro
BS 15+ years, MS 13+ years, PhD 11+ years
Experience with 56G PAM4, 25G NRZ SerDes technologies a plus