Actalent Wayne , NJ 07470
Posted 1 week ago
Description:
The scope of work consists of Design Verification of VHDL developed for an FPGA. The task will include DV planning (i.e., verification and coverage plan development), creation of test bench infrastructure - whether from scratch or through re-use of existing code - testcase development, testing, debug, and coverage closure. All DV code will be developed using best practices. Team leadership responsibilities may also be required for this role (schedule development/tracking, resource allocation, technical guidance, etc).
Tasks to include:
1.Coverage and Verification plan documents describing verification flows and constructs, functionality to be verified, and testbench usage
2.Work Breakdown Structure (WBS), Gantt charts and/or other forms of a plan showing task breakdown, duration estimates, hand-ins, milestones, and task assignments;
3.SV/UVM Testbench infrastructure - environment, UVCs, monitors, predictors, checkers, coverage collectors - required for verifying the VHDL implementing FPGA functionality.
4.SV/UVM testcases for configuring the testbench and for generating the stimulus needed to verify the VHDL implements the functionality described in the FPGA specification.
5.Associated scripts and flows necessary for verification and simulation
6.Issue tracking to ensure all issues uncovered are resolved satisfactorily.
7.Revision / release control of all design verification source code and documentation produced as described in items 3.1.1 thru 3.1.4, above
8.Code and functional coverage reporting
Skills:
Fpga, Asic, Verilog, Design verification, UVM, Systemverilog, Xilinx, Vhdl
Top Skills Details:
Fpga,Asic,Verilog,Design verification,UVM,Systemverilog
Additional Skills & Qualifications:
Active Secret Clearance
1.Required Design Tools and Revisions
2.All tools in sections items 2 and 3 (below) will be provided by BAE Systems.
3.Mentor tool set:
Qualifications:
1.SV/UVM Testbench infrastructure - environment, UVCs, monitors, predictors, checkers - and testcases needed for verifying the VHDL implementing FPGA functionality
2.Scripts, constraints, setup, or other associated files related to the testbench
3.Coverage and Verification plan documents describing verification flows and constructs, functionality to be verified, and testbench usage
4.Code and functional coverage reports
Experience Level:
Intermediate Level
About Actalent
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Actalent