Fpga Design Engineer

Teradyne San Jose , CA 95111

Posted 5 months ago

Duties & Responsibilities

Teradyne is a global technology company delivering progressive solutions to complex testing challenges. Without creativity and the diversity of thought, Teradyne's technological innovations would not leave the ground. If you are excited at the prospect of joining a global team, that is both exciting and dynamic, then Teradyne may be the place for you!

In San Jose, California we are developing test instrumentation for some of the world's most advanced and highest performance integrated circuits. Our products integrate state-of-the-art digital and analog designs using leading edge ASIC and FPGA technologies, liquid cooling, and high density / high performance signal delivery.

We are a small, close-knit team working in an exciting focused atmosphere. We are looking for an experienced FPGA design engineer with outstanding technical skills and leadership potential. The candidate should have a strong desire to contribute to a team oriented project where what matters most is our success in bringing products to market quickly with exceptional quality and reliability.

Duties include:

  • Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.

  • Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.

  • Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.

  • Maintain schedule commitments and deliver high quality end products.

  • Occasional travel may be required.

Basic Qualifications, Experience, Skills & Education Required

The Senior FPGA Design Engineer position requires a Bachelors Degree in Electrical Engineering with a minimum of 5 years of relevant work experience or Masters Degree in Electrical Engineering with a minimum of 3 years of relevant experience in ASIC / FPGA Verilog HDL digital logic design techniques and related verification activities.

Candidate should be an expert with constraint generation for synthesis and timing closure techniques; be familiar with high speed SerDes interfaces, have experience with and high speed memory subsystems. Candidate should have design experience with various FPGAs and/or ASIC technologies.

Candidate should also have participated in module/PCBA design and engineering lab checkout. Candidate has acted as technical lead for various design and verification tasks.

Additional Skills:

Familiarity with automatic semiconductor test equipment and the various subsystems contained within is highly desirable. In particular, an understanding of the integration of ATE subsystems into FPGA designs. Lab experience including use of oscilloscopes, logic analyzers, protocol analyzers preferred.

#LI-MSTER

Teradyne is a leading supplier of automation equipment for test and industrial applications. Teradyne Automated Test Equipment (ATE) is used to test semiconductors, wireless products, data storage and complex electronic systems, which serve consumer, communications, industrial and government customers.

Our Industrial Automation products include Collaborative Robots used by global manufacturing and light industrial customers to improve quality and increase manufacturing efficiency. In 2017, Teradyne had revenue of $2.14 billion and currently employs approximately 4,800 people worldwide.

Our stock is listed on the Nasdaq Global Select Market under the symbol TER.



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