Formal Verification Engineer
Austin , TX 78719
Posted 3 months ago
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Job Description: Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world.
We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced Hardware Design Engineers to build the next generation of our cloud server infrastructure. Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies.
As a member of the Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you'll work with thought leaders in multiple technology areas.
You'll have relentlessly high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve your products performance, quality and cost. We're changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.
Verify that our silicon solutions will achieve the functionality needed to enable our customers Develop a deep understanding of microarchitectural design details Define meaningful formal properties that capture the design intent Collaborate and communicate effectively with RTL design and verification engineers Analyze bounded proof results and write functional coverage points Develop creative solutions for abstraction methods, and FV checking algorithms to obtain deeper proofs Basic Qualifications BS degree or higher in EE or CE or CS 3+ years or more of experience in pre-silicon functional verification. 1+ years of experience in formal verification, utilizing industry standard tools such as JasperGold or VC Formal.
Experience developing formal verification plans and executing those plans to closure. Able to code in Verilog / System Verilog Preferred Qualifications Ability to read, interpret and provide feedback on architectural and micro-architectural specifications. Experience debugging formal verification failures. Ability to develop and deploy FV methodologies Understand complex FV checking and abstraction strategies Ability to implement assertions and write functional coverage points Experience with constrained random stimulus generation Proficiency in a scripting language and automation