As a Hardware Engineer you will be a member of the Implementation team designing the next generation high-performance processor chips in leading edge CMOS process technology, targeted at network and consumer applications. You will be required to maintain, enhance, and support Cavium's Place and Route Flow incorporating industry standard EDA tools You will perform synthesis, floorplanning, place and route, timing analysis, and closure on complex logic blocks.
You will develop and implement timing and logic ECO's. You will interface with the RTL design team to drive design modifications to resolve congestion and timing issues. You will work with the global timing team in debugging/resolving any block level timing issues seen at full chip.
You will test and maintain chip end-to-end flows, with specific focus on place and route and timing. You will interface with tool vendors to drive tool fixes and improvements in support of on-going and planned CAD activities. You might also perform tool evaluations of new vendor tools and functions. #LI-KB1 #GLDR Bachelors degree in Computer Science, Electrical Engineering or related fields +3 yrs experience or a Master's +0 years experience.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.