Do you want to utilize your background to make big things happen? Can you deliver on a predictable and dynamic schedule? Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Library Layout Designers. In this highly visible role, you will be a member of Apple's custom layout team, working on the latest technology nodes to create extraordinary libraries. This is a fast paced work environment with endless learning opportunities working in the design team with members of integration, CAD, circuit and technology engineering.
We are looking for applicants with 5+ years experience in library layout design of deep SubMicron CMOS circuits used in high performance microprocessors.
Experience designing low noise, low power library cells.
High level proficiency in device floorplanning, interface planning and area optimization of library cells.
Good understanding of issues with RC delay, electromigration, self heating and cross capacitance.
Recognize failure prone circuit and layout structures, dedicatedly work with designers for the best approach to problems.
Great skills on interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
Knowledge of CADENCE VXL layout tools.
Scripting skills in PERL or SKILL or CSH are considered a plus, but not required.
Excellent communication skills and able to work with multi-functional teams.
Managing, tracking and running regression on multiple cells.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. As a member of the layout team of the microprocessor group, you will be responsible to deliver PDV clean layout, including the following: Designing complex layout of custom library cells used in P&R and custom IP development. Reviewing and analyzing floorplans and complex circuits with circuit designers. Running a complete set of design verification tools available on completed library cells. Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Interpretation of LVS, DRC and ERC report to find fastest way to complete layouts. Exceed engineering specifications and expectations. Utilize advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits.
Education & Experience