Digital Design & Verification Engineer, University Grad, FRL

Facebook Menlo Park , CA 94025

Posted 3 months ago

Facebook Reality Labs brings together a world-class team of researchers, developers, and engineers to create the future of virtual and augmented reality, which together will become as universal and essential as smartphones and personal computers are today. And just as personal computers have done over the past 45 years, AR and VR will ultimately change everything about how we work, play, and connect.

We are developing all the technologies needed to enable breakthrough AR glasses and VR headsets, including optics and displays, computer vision, audio, graphics, brain-computer interface, haptic interaction, eye/hand/face/body tracking, perception science, and true telepresence. Some of those will advance much faster than others, but they all need to happen to enable AR and VR that are so compelling that they become an integral part of our lives.

As a Digital Design and Digital Verification Engineer, you will work with a world-class group of researchers and engineers and use your digital design and/or verification skills to contribute to development and optimization of algorithms in hardware. You could also be involved in the design and implementation of the testing infrastructure to verify these new core IP designs.

RESPONSIBILITIES

  • Work with researchers and architects in algorithm analysis, optimization and identification of optimal digital Architectures for their implementation

Implement and verify optimal design modules leading to FPGA emulation and ASIC implementation

Work with researchers and architects defining and implementing verification methodologies

Support or lead defining the infrastructure and architecture of the different core IPs

Define and track detailed test plans for the different modules and top levels

Implement scalable test benches including checkers, reference models, and coverage groups in SystemVerilog

Keep track of coverage metrics and bugs encountered and fixed

Implement self-testing directed and random tests

Develop the scripts and code necessary for proper automation

Support post silicon bringup and debug activities

MINIMUM QUALIFICATIONS

  • Currently has, or is in the process of obtaining a Bachelors or Masters degree in Electrical Engineering, Computer Science or related technical field

Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment

Experience in digital design using Verilog, SystemVerilog or VHDL

Experience in Digital Design Verification (DV) using System Verilog and OVM/UVM

C, C++ coding, debugging experience

PREFERRED QUALIFICATIONS

  • Experience in clock management, clock domain crossing and reset architectures

Experience in ASIC/FPGA design methodologies

Experience in digital ASIC architecture and Architecture

Experience in Python, Perl, shell scripting

Facebook is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may contact us at accommodations-ext@fb.com.


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Digital Design & Verification Engineer, University Grad, FRL

Facebook