Digital Design Verification Engineer

Promedia San Diego , CA 92101

Posted 1 week ago

Scope of work:
We are seeking gifted engineers who have experience in developing digital architectures and hardware designs in the aforementioned functional areas. This role will involve specification, system level architecture and micro-architecture of digital hardware as well as working with IP design teams, SoC HW and SW teams to ensure the solutions are implemented efficiently and are meeting specification. A successful candidate will have experience working with ARM-based SoC architectures, in-depth understanding of computer architecture fundamentals, the ability to develop complex systems, and the communication and collaboration skills to work with a large world-wide design organization.

Responsibilities:
Test planning, test bench development, test development, debug failures and report bugs, achieve coverage closure.
Minimum skills required:
Strong critical thinking, problem-solving and test planning skills. General knowledge of ASIC design and verification tools, techniques and methodology Requires a minimum of 4+ years industry experience in RTL design verification Solid understanding of design and verification languages: RTL, SystemVerilog, SystemVerilog Assertions (SVA), VHDL, Verilog Experience and understanding of advanced verification methodologies such as OVM/UVM Very good communication, team work and collaboration skills
Education:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics and communications engineering, Computer science.
Good to have skills:
Experience developing from scratch block level testbench environment using SystemVerilog and OVM/UVM Experience closing functional and code coverage of any digital design block Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile Experience using revision management (e.g. Clearcase, CVS, & DesignSync)
Duration: 12 months+
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Digital Design Verification Engineer

Promedia