Design Verification - Senior Staff Engineer

Mastech Digital, Inc. San Jose , CA 95111

Posted 2 weeks ago

Location: San Jose, CA Job Code: 219711 Posted: Oct 06, 2020 Description:

Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Design Verification

  • Sr. Staff Engineer for our client in the IT-Services/Technology domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract position and the client is looking for someone to start immediately.

Duration: 6 Months Contract

Location: San Jose, CA and Phoenix, AZ (Remote till Covid-19 Ends)

Role: Design Verification

  • Sr. Staff Engineer

Primary Skills:Infrastructure

Role Description: The Design Verification

  • Sr. Staff Engineer must have at least 05+ years of experience. For this role, you must be a SoC Design Verification Engineer to provide design verification services for multi CPU/DSP SoC.

Responsibilities:

  • Testbench development
  • System Verilog UVM and C tests
  • Integration/development of C tests/APIs and SW build flow

  • Integration/development of UVM mailboxes and HW/SW communication components

  • Integration of lower level UVM testbenches

  • Test plan development

  • Power Aware testbench development and simulations

  • Seamless porting between simulation/emulation/prototyping platforms

  • Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto

  • Coverage collection and closure

  • Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Minimum Qualifications:

  • 7+ years of experience in RTL Design and Verification area of which 5+ years of experience in SoC Design Verification and HW/SW verification

  • Deep knowledge of System Verilog UVM and vertical testbench integration

  • Knowledge of low level HW/SW interaction and debug

  • Knowledge of multi CPU and debug architectures

  • Experience with development of fully automated flows

Preferred Qualification:

  • Experience with low level SW debug - disasm, Tarmac, trace

  • Experience with coresight architecture

  • Experience with embedded SW low level concepts and debug

  • Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
  • Experience with coverage merging across simulation and emulation

  • Experience with Power Aware and Gate Level Netlist in Emulation

  • Experience with development of fully automated flows

  • Experience with Gate Level Simulations

  • Python Scripting

Education: Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Information Technology or another related field or Equivalent.

Experience: Minimum 05+ years

Relocation: This position will not cover relocation expenses

Travel: No

Local Preferred: Yes

Recruiter Name: Himanshu Prashar

Recruiter Phone: 412 436 0333 (Ext: 2084)

Equal Employment Opportunity

icon no score

See how you match
to the job

Find your dream job anywhere
with the LiveCareer app.
Mobile App Icon
Download the
LiveCareer app and find
your dream job anywhere
App Store Icon Google Play Icon
lc_ad

Boost your job search productivity with our
free Chrome Extension!

lc_apply_tool GET EXTENSION

Similar Jobs

Want to see jobs matched to your resume? Upload One Now! Remove
Senior Design Verification Engineer

Xilinx, Inc.

Posted 2 weeks ago

VIEW JOBS 10/7/2020 12:00:00 AM 2021-01-05T00:00 At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives. If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX. Job Description Description This is an exciting opportunity to work in the Xilinx SOC Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on full chip, system level verification, silicon bring up in the lab Responsibilities: * Create block level verification plan, test plans and subsystem test plan * Develop block level test bench and tests in UVM methodology including scoreboard. * Work on subsystem level verification * Work with designers to get the coverage closure * Port the block level tests to sub system test bench * Integrate VIPs as needed * Work with software, validation and emulation teams as needed. * Work on other aspects of verification like CDC, gate simulation and formal verification * Work on lab bring up as needed #mh Job Qualifications * MS with 2 years of exp in Electrical Engineering or Computer Engineering or related equivalent * -Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology. * -Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team * -Good understanding of object oriented programming concepts. * -Prior experience in working on caching protocols such as ACE and CHI. * -Prior experience in verifying is system/sub system level involving multiple blocks. * - -Prior experience with protocols such as AXI, APB, AHB etc. * -Programming in scripting languages like Python, TCL and Perl. * -Excellent communication skills * -Good problem solving skills and analytical ability * -Familiarity with EDA tools for simulation, debugging, coverage analysis, formal verification, CDC, LINT etc. * Desirable Qualifications: * -Understanding of FPGA architecture * -Prior experience in high speed serial protocols such PCIE, CXL and 10G Ethernet * --Prior experience in working on caching protocols such as ACE and CHI. * -Prior experience with ARM based Socs * -Exposure to formal verification methodologies * -Understanding of ARM architecture and assembly language programming * -Prior experience in integrating Verification IPs (VIP) & UVC in verification environment. * -Prior experience in bringing up gate level simulation and debugging issues. Xilinx, Inc. San Jose CA

Design Verification - Senior Staff Engineer

Mastech Digital, Inc.