Design Verification - Senior Staff Engineer

Mastech Digital, Inc. San Jose , CA 95111

Posted 2 weeks ago

Location: San Jose, CA Job Code: 219711 Posted: Oct 06, 2020 Description:

Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Design Verification

  • Sr. Staff Engineer for our client in the IT-Services/Technology domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract position and the client is looking for someone to start immediately.

Duration: 6 Months Contract

Location: San Jose, CA and Phoenix, AZ (Remote till Covid-19 Ends)

Role: Design Verification

  • Sr. Staff Engineer

Primary Skills:Infrastructure

Role Description: The Design Verification

  • Sr. Staff Engineer must have at least 05+ years of experience. For this role, you must be a SoC Design Verification Engineer to provide design verification services for multi CPU/DSP SoC.


  • Testbench development
  • System Verilog UVM and C tests
  • Integration/development of C tests/APIs and SW build flow

  • Integration/development of UVM mailboxes and HW/SW communication components

  • Integration of lower level UVM testbenches

  • Test plan development

  • Power Aware testbench development and simulations

  • Seamless porting between simulation/emulation/prototyping platforms

  • Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto

  • Coverage collection and closure

  • Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Minimum Qualifications:

  • 7+ years of experience in RTL Design and Verification area of which 5+ years of experience in SoC Design Verification and HW/SW verification

  • Deep knowledge of System Verilog UVM and vertical testbench integration

  • Knowledge of low level HW/SW interaction and debug

  • Knowledge of multi CPU and debug architectures

  • Experience with development of fully automated flows

Preferred Qualification:

  • Experience with low level SW debug - disasm, Tarmac, trace

  • Experience with coresight architecture

  • Experience with embedded SW low level concepts and debug

  • Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
  • Experience with coverage merging across simulation and emulation

  • Experience with Power Aware and Gate Level Netlist in Emulation

  • Experience with development of fully automated flows

  • Experience with Gate Level Simulations

  • Python Scripting

Education: Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Information Technology or another related field or Equivalent.

Experience: Minimum 05+ years

Relocation: This position will not cover relocation expenses

Travel: No

Local Preferred: Yes

Recruiter Name: Himanshu Prashar

Recruiter Phone: 412 436 0333 (Ext: 2084)

Equal Employment Opportunity

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