What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the "extra mile" to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
Our group is an IP group which caters to multiple SoCs DFT/Test requirements, working with the Product Engineering and debug is our prime goal. We have an exciting opportunity
for candidates who has the ability to understand the circuits and extract the implications on DFT modeling, analyze how testability and fault analysis work. At any given time
the successful candidate will get exposure to test/scan/debug architecture, to RTL to DV and scan timing.
As a Senior Design Engineer, you will work closely with mixed signal IP DFT and Verification teams to develop state of the art mixed signal Phy IP. You will work with both DFT and verification teams to quantify the structural test qualify of the IP and take it to desired level.
You will work to drive innovation as by tackling challenging problems for the latest mixed signal IPs on latest technology nodes. As a Senior Design Engineer, you will quantify the structural test coverage for the high speed SERDES IPs using commercial fault simulator tools
The successful candidate's minimum qualifications will include the following:
o BSEE or MSEE with min 3 years of verification or DFT experience
o Experience with high-speed SERDES, such as PCIe Phy is desirable
o Strong background in Design-for-Test concepts, System Verilog, VMM/UVM and C/C++
o Experience with Verilog and System Verilog design of complex IP blocks working with high speed design
o Experience in test/scan/debug architecture verifying design-for-test DFT logic would be an asset
o Experience with Fault simulation tools (analog or digital) would be considered an asset Ex. Synopsys ZOIX tool or others.
Requisition Number: 67894
Country: United States State:
California City: Santa Clara
Job Function: Design
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