Ampere is designing the future of hyperscale cloud and edge computing with its 64-bit Arm server processor architecture. Born in and built for the cloud with a modern architecture, Ampere gives customers the freedom to accelerate the delivery of the most memory-intensive applications such as artificial intelligence, big data, machine learning and databases in the cloud. The Ampere eMAG family of products delivers the highest memory throughput and lowest TCO tailored for the emerging growth of cloud computing and next-generation data centers.
Like the scientist behind its name, Ampere employees are innovators. We understand the needs of cloud computing and different software requirements. We are inventing what comes next and looking at everything from the structure of memory and how efficient the system is, to considerations on speed, cost of electricity and ability to cool. Power, size, weight and cost are driving the technology requirements and the innovation to come.
Our world class team of engineers, with depth and expertise in the cloud and semiconductor industries, is not only focused on the development of new semiconductor designs but also building out the first software ecosystem for Arm-based server processors. Through the Ampere approach to the cloud and edge, we give our customers the freedom to challenge the status quo and accelerate next-generation data centers for the most memory-intensive applications. Given the challenge we have outlined, we are building a culture of entrepreneurs that ensure customers come first, proactively approaching industry challenges in the areas of security, power and performance, delivering results that matter most.
We are looking for an experienced SerDes/IO Circuit Design Engineer to join a small but growing Processor Design group, advancing the art of high-performance circuit design.
Ideal candidates will channel their creativity to develop a design with logic and physical design architects that will improve the system. They will have design flexibility and end-to-end ownership responsibilities to make highly visible contributions.
Evaluate and provide feedback on state of the art SerDes and other IO circuit IP from various IP vendors for use in a cloud-computing server SOC in bleeding edge process technology nodes
Understand system needs and assess specifications for IP requirements, and provide feedback to architecture team on design feasibility
Act as a technical liaison to communicate needs to vendors, and assess vendor IP for design and schedule risks
Work with logic, physical design and packaging teams to develop a robust integration strategy of vendor IP to ensure a successful product
Develop validation strategy for IP circuit and overall system to function as designed in post-silicon lab measurement and characterization environment
Role could transition to designing and developing custom IP in-house to meet specifications based on customization needs vs. vendor IP availability
Minimum 10 years of relevant work experience
Strong understanding of analog and mixed signal design techniques as well as SI/PI concepts of SerDes and IO IPs
Demonstrated hands on project design, implementation and delivery experience
Experience with cadence design suite for schematic, layout and Spice simulations
Experience with physical design integration and optimization, functional debug and post-layout netlists