CAD Formal Verification Engineer

Qualcomm San Diego , CA 92140

Posted 2 months ago

Job Detail

Job Id E1980868 Job Title CAD Formal Verification Engineer Post Date 02/14/2020 Company Qualcomm Technologies, Inc.

Job Area Engineering

  • Hardware

Location California

  • San Diego

Job Overview

Qualcomm Technologies Incs global CAD team develops tools, flows, and methodologies for different aspects of RTL design and verification. RTL verification includes simulations as well as formal verification.

This position is about the formal verification tools, flows, and methodology, and includes the following activities:

Work with industry-standard formal tools for model checking as well as equivalence checking Implement tools for automation of the formal verification property generation Develop and enhance formal verification flows, formal test plans, and methodology Collaborate with design engineers, 3rd party EDA tool vendors, as well as other CAD engineers Participate in project proposal development including key milestones and deliverables Execute, deliver and support project goals in a timely manner Resolve issues in all phases of development to assure smooth project execution" id="hdnJobOverview" />Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning.

It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.

Qualcomm Technologies Incs global CAD team develops tools, flows, and methodologies for different aspects of RTL design and verification. RTL verification includes simulations as well as formal verification.

This position is about the formal verification tools, flows, and methodology, and includes the following activities:

Work with industry-standard formal tools for model checking as well as equivalence checking Implement tools for automation of the formal verification property generation Develop and enhance formal verification flows, formal test plans, and methodology Collaborate with design engineers, 3rd party EDA tool vendors, as well as other CAD engineers Participate in project proposal development including key milestones and deliverables Execute, deliver and support project goals in a timely manner Resolve issues in all phases of development to assure smooth project execution All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field.

5+ years ASIC design, verification, or related work experience." id="hdnMinimumQualifications" />Bachelor's degree in Science, Engineering, or related field.

5+ years ASIC design, verification, or related work experience. Preferred Qualifications Required Hardware knowledge:

Knowledge of hardware description languages: Verilog, VHDL, System C Knowledge of RTL design and architecture: multicore SoC architectures, Network on Chip, state machines and control logics, registers, timing and concurrency, etc.

Required Software knowledge:

Strong experience with at least one programming or scripting language: C++, java, java script, perl, python, TCL, VB, etc. Understanding of data structures, algorithms, and software design principles


Required Formal Verification

Knowledge:

Strong knowledge of formal verification: model checking, equivalence checking, system verilog assertions, assumptions, and cover properties Some experience with using of a formal tool: Jasper, IFV/IEV, VCF

Preferred Qualificaitons

Worked as a formal verification engineer in industry; knowing how to formally prove an RTL design using system verilog assertions Fully understand AMBA standard bus protocols: AHB, AXI3, AXI4, ACE Vast experience in tool development using python, java script, perl, tcl.

Working knowledge of electronic design automation (EDA) and verification flows Excellent problem-solving skills: able to work and drive practical solutions under research environment Good communication skills and personal skills in a multi-disciplinary, collaborative, fast pace engineering environment Ph.D. in Computer Science or Computer Engineering " id="hdnPreferredQualifications" />Required Hardware knowledge:

Knowledge of hardware description languages: Verilog, VHDL, System C Knowledge of RTL design and architecture: multicore SoC architectures, Network on Chip, state machines and control logics, registers, timing and concurrency, etc.

Required Software knowledge:

Strong experience with at least one programming or scripting language: C++, java, java script, perl, python, TCL, VB, etc. Understanding of data structures, algorithms, and software design principles


Required Formal Verification

Knowledge:

Strong knowledge of formal verification: model checking, equivalence checking, system verilog assertions, assumptions, and cover properties Some experience with using of a formal tool: Jasper, IFV/IEV, VCF

Preferred Qualificaitons

Worked as a formal verification engineer in industry; knowing how to formally prove an RTL design using system verilog assertions Fully understand AMBA standard bus protocols: AHB, AXI3, AXI4, ACE Vast experience in tool development using python, java script, perl, tcl.

Working knowledge of electronic design automation (EDA) and verification flows Excellent problem-solving skills: able to work and drive practical solutions under research environment Good communication skills and personal skills in a multi-disciplinary, collaborative, fast pace engineering environment Ph.D. in Computer Science or Computer Engineering Education Requirements Preferred: Doctorate, Computer Engineering and/or Computer Science" id="hdnEducationalRequirements" />Required: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering

Preferred: Doctorate, Computer Engineering and/or Computer Science Keywords Electronic Design Automation (EDA), CAD, Formal Verification, Model Checking, Equivalence Checking, System Verilog Assertion, Python, Perl, Java Scrip, TCL;



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CAD Formal Verification Engineer

Qualcomm