Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
3 years of hardware industry experience or equivalent PhD research experience.
Experience with low-power techniques (e.g., dynamic and leakage power estimation, optimization techniques such as clock-gating, etc.).
5 years of experience in Register-Transfer Level (RTL) design and low-power design techniques.
Experience with scripting, algorithmics, and familiarity with machine learning and data mining concepts.
Experience in low-power design methodology, related tools and flows (e.g., RTL power analysis, estimation, optimization, fast replay simulation flow, power profiling, PTPX).
Knowledge of low-power design structures and constructs.
Knowledge of CPU microarchitecture.
About the job
As a CAD and Design Methodology Architect, you will be the pillar of the CPU Low-Power Design team. You will architect, implement, and deploy the new platform infrastructure and methodology to support all power activities for the next generation CPU.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Define and implement the infrastructure to support all power activities including energy modeling, roll-ups, weekly regression, early power analysis, predictions, and trends.
Collaborate with the CAD CPU team on tool evaluations and flows.
Develop database and advanced queries to support weekly power regression.
Develop novel heuristics and advanced techniques in collaboration with the CAD and Design Verification teams on early power estimation, fast simulation, power analysis, and roll-ups.
Leverage machine-learning and data mining techniques to deploy solutions to support CPU energy modeling activities.