Asic/Soc Silicon Design-For-Test Lead

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) lead to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for leading the delivery of built-in test functions for performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies in leading-edge process nodes.

Responsibilities include:

• Own MatX's DFT methodology and collaborate on the silicon design and physical design methodology with a scalable solution across blocks, subsystems, fullchip designs from RTL to GDS.

• Architect the DFT solution including memory testability and repair, logic test for coverage of structural and at-speed testability for very large and complex silicon using industry-leading DFT tools and flows

• Select top-level DFT control structures to drive efficient block and subsystem level DFT implementation optimizing for DFT cost and resulting coverage

• Plan and drive intermediate and sign-off reviews as well as execution progress reporting based on key metrics-tracking towards various silicon milestones including design freeze and tapeout

• Work closely with the design, verification and physical design co-owners of the subsystem/block and top-level on DFT verification and physical design considerations to deliver best-in-class performance-power-area results

• Leading design services partners and other critical third-party vendors and partners on planning and executing block-level and chip-level DFT

• Working with Operations, foundry and test partners to bring up test program on silicon and meeting all coverage goals on silicon towards production and NPI

Requirements:

• Architecture-to-production experience in driving DFT strategy and execution on large and complex ASICs and SOCs to production silicon

• Production-proven experience with deploying DFT at-scale for large and high-performance ASICs and SOCs in both pre0-silicon implementation and post-silicon test program completion for NPI

• Project experience in collaborating with design, verification and physical design teams to structure and partition the design optimally for PPA and sign-off

• Experience in working with a third-party design services partners to deliver tapeout-ready designs with DFT

• Experience with test engineering partners and taking test programs from bring up to volume production

• Experience with FA (Failure Analysis) and debugging failures on silicon with design and verification teams

Compensation: The US base salary for this full-time position is $120,000 - $400,000 + equity + benefits

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.